AN983 datasheet(5/91 Pages) ETC

5 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

CSR26 (offset = a8h) - PAR1, physical address register 1............................... 44

CSR27 (offset = ach) - MAR0, multicast address register 0 ............................ 45

CSR28 (offset = b0h) - MAR1, multicast address register 1............................ 45

Operation Mode Register (Memory base offset 0FCh) .................................... 46

7.3. PHY Registers (ACCESSED by csr9 MDI/MMC/MDO/MDC) ......................... 47

7.3.1. Transceiver registers Descriptions .......................................................... 47

7.4. Descriptors and Buffer Management................................................................. 51

7.4.1 Receive descriptor.................................................................................... 52

7.4.1.1 Receive Descriptor Table.............................................................. 52

7.4.1.2 Receive Descriptor Descriptions................................................... 52

RDES0 .............................................................................................................. 52

RDES1 .............................................................................................................. 53

RDES2 .............................................................................................................. 53

RDES3 .............................................................................................................. 53

7.4.2. Transmit Descriptor ................................................................................ 53

7.4.2.1. Transmit Descriptor Table ........................................................... 53

7.4.2.2. Transmit Descriptor Descriptions ................................................ 54

TDES0............................................................................................................... 54

TDES1............................................................................................................... 54

TDES2............................................................................................................... 55

TDES3............................................................................................................... 55

8. FUNCTIONAL DESCRIPTIONS............................................................................. 56

8.1 Initialization Flow............................................................................................... 56

8.2 Network Packet Buffer Management .................................................................. 57

8.2.1 Descriptor Structure Types ...................................................................... 57

8.2.2 The point of descriptor management ....................................................... 59

8.3 Transmit Scheme and Transmit Early Interrupt ................................................. 61

8.3.1 Transmit flow........................................................................................... 61

8.3.2 Transmit pre-fetch data flow.................................................................... 61

8.3.3 Transmit early interrupt Scheme.............................................................. 62

8.4 Receive scheme and Receive early interrupt scheme.......................................... 63

8.5 Network Operation.............................................................................................. 65

8.5.1 MAC Operation ....................................................................................... 65

8.5.2 Transceiver Operation.............................................................................. 66

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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