8

7

6

5

4

3

2

1

Exposed Pad on Bottom

Connect to Ground

FB

GND

ADJ

PGATE

ISEN

VCC

RT

VIN

1

2

3

4

5

8

7

6

Exposed Pad on Bottom

Connect to Ground

FB

PGATE

ISEN

GND

VCC

ADJ

RT

VIN

1

2

3

4

5

8

7

6

FB

PGATE

ISEN

GND

VCC

ADJ

RT

VIN

LM25085A

SNVS601B – JANUARY 2009 – REVISED MARCH 2013

www.ti.com

Connection Diagram

Figure 1. Top View

Figure 2. Top View

8-Lead HVSSOP

8-Lead VSSOP

Figure 3. Top View

8-Lead WSON

PIN DESCRIPTIONS

Pin

Name

Description

Application Information

No.

1

ADJ

Current Limit Adjust

The current limit threshold is set by an external resistor from VIN to ADJ in

2

RT

On-time control and shutdown

An external resistor from VIN to RT sets the buck switch on-time and switching

frequency. Grounding this pin shuts down the controller.

3

FB

Voltage Feedback from the

Input to the regulation and over-voltage comparators. The regulation level is 0.9V.

regulated output

4

GND

Circuit Ground

Ground reference for all internal circuitry

5

ISEN

Current sense input for current

limit detection.

source and the sense resistor when using a current sense resistor.

6

PGATE

Gate Driver Output

Connect to the gate of the external PFET.

7

VCC

Output of the gate driver bias

Output of the negative voltage regulator (relative to VIN) that biases the PFET gate

regulator

driver. A low ESR capacitor is required from VIN to VCC, located as close as

possible to the pins.

8

VIN

Input supply voltage

The operating input range is from 4.5V to 42V. A low ESR bypass capacitor must be

located as close as possible to the VIN and GND pins.

EP

Exposed Pad

Exposed pad on the underside of the package (HVSSOP-PowerPAD-8 and WSON

only). This pad is to be soldered to the PC board ground plane to aid in heat

dissipation.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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