Unused Input

Input

Output

Output

Input

Unused Input

0

10

20

30

40

50

60

70

80

90

100

2

3

4

5

6

V

CL 50pF

CL 150pF

C002

13

SN54HC244, SN74HC244

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SCLS130E – DECEMBER 1982 – REVISED MAY 2016

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Copyright © 1982–2016, Texas Instruments Incorporated

Typical Application (continued)

9.2.3 Application Curve

Figure 7. Enable Time

10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions.

supply, TI recomments a 0.1-

0.022-

μF capacitors for each power terminal. It is ok to parallel multiple bypass capacitors to reject different

frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The

bypass capacitor should be installed as close to the power terminal as possible for the best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of

digital logic devices are unused. Some examples are when only two inputs of a triple-input and gate are used, or

when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the

undefined voltages at the outside connections result in undefined operational states.

Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic

devices must be connected to a high or low bias to prevent them from floating. The logic level that should be

applied to any particular unused input depends on the function of the device. Generally they will be tied to GND

11.2 Layout Example

Figure 8. Layout Diagram