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2 x VP x VL

L x 'IO

CO t

VP x VL

L x 'IO

CO t

1 +

1 -

RC x 'IO

VP x VL

L x 'IO

CO t

RC d

'IO

'IL

PCO = RC x

VP =

L x 'IO

2 x CO x VL

x CO x VL

2 x L

LM3000

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SNVS612B – JULY 2009 – REVISED APRIL 2013

The amount of output ripple that can be tolerated is application specific. A general recommendation is to keep

the output ripple less than 1% of the rated output voltage. The output capacitor selection will also affect the

output voltage droop and overshoot during a load transient. The peak transient of the output voltage during a

load current step is dependent on many factors. Given sufficient control loop bandwidth an approximation of the

transient voltage can be obtained from:

where

•

VP (V) is the output voltage transient

•

ΔIO (A) is the load current step change

(26)

CO (F) is the output capacitance, L (H) is the value of the inductor and RC (Ω) is the series resistance of the

output capacitor. VL (V) is the minimum inductor voltage, which is duty cycle dependent.

For D < 0.5, VL = VOUT

For D > 0.5, VL = VIN - VOUT

This shows that as the input voltage approaches VOUT, the transient droop will get worse. The recovery

overshoot remains fairly constant.

The loss associated with the output capacitor series resistance can be estimated as:

(27)

Output Capacitor Design Procedure

For the design example VIN = 12V, VOUT = 3.3V, D = VOUT / VIN = 0.275, L = 2.7 μH, ΔIL = 1.8A, ΔIO = 8A and VP

= 0.15V.

To meet the transient voltage specification, the maximum RC is:

(28)

For the design example, the maximum RC is 18.75 mΩ. Choose RC = 15 mΩ as the design limit.

From the equation for VP, the minimum value of CO is:

(29)

For D < 0.5, VL = VOUT

For D > 0.5, VL = VIN - VOUT

With RC = VP / ΔIO this reduces to:

(30)

With RC = 0 this reduces to:

(31)

Since D < 0.5, VL = VOUT. With RC = 15 mΩ, the minimum value for CO is 218 μF.

The minimum control loop bandwidth fC is given by:

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