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PCA9545 Datasheet(PDF) 2 Page - NXP Semiconductors |
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PCA9545 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 14 page ![]() Philips Semiconductors Product data PCA9545 4-channel I2C switch with interrupt logic and reset 2 2002 Mar 28 853-2302 27940 FEATURES • 1-of-4 bi-directional translating switches • I2C interface logic; compatible with SMBus standards • 4 active low interrupt inputs • Active low interrupt output • Active low reset input • 2 address pins allowing up to 4 devices on the I2C bus • Channel selection via I2C bus, in any combination • Power up with all switch channels deselected • Low RDS ON switches • Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses • No glitch on power-up • Supports hot insertion • Low stand-by current • Operating power supply voltage range of 2.3 V to 5.5 V • 5 V tolerant Inputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115 and 1000 V per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Package Offer: SO20, TSSOP20 DESCRIPTION The PCA9545 is a quad bi-directional translating switch controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of the four interrupt inputs. An active-LOW reset input allows the PCA9545 to recover from a situation where one of the downstream I2C buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C state machine and causes all the channels to be deselected as does the internal power on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9545. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. PIN CONFIGURATION A0 A1 RESET INT0 SD1 VDD SDA SCL 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 SD0 SC0 INT1 INT SC3 SD3 INT3 SC2 9 12 10 11 SC1 VSS SD2 INT2 SW00762 Figure 1. Pin configuration PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 A0 Address input 0 2 A1 Address input 1 3 RESET Active low reset input 4 INT0 Active low interrupt input 0 5 SD0 Serial data 0 6 SC0 Serial clock 0 7 INT1 Active low interrupt input 1 8 SD1 Serial data 1 9 SC1 Serial clock 1 10 VSS Supply ground 11 INT2 Active low interrupt input 2 12 SD2 Serial data 2 13 SC2 Serial clock 2 14 INT3 Active low interrupt input 3 15 SD3 Serial data 3 16 SC3 Serial clock 3 17 INT Active low interrupt output 18 SCL Serial clock line 19 SDA Serial data line 20 VDD Supply voltage ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 20-Pin Plastic SO –40 to +85 °C PCA9545D SOT163-1 20-Pin Plastic TSSOP –40 to +85 °C PCA9545PW SOT360-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. |
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