PCM1770

PCM1771

SLES011C – SEPTEMBER 2001 – REVISED MAY 2004

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13

DETAILED DESCRIPTION

SYSTEM CLOCK, RESET, AND FUNCTIONS

System Clock Input

The PCM1770 and PCM1771 devices require a system clock for operating the digital interpolation filters and multilevel

∆-Σ

modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system clock frequencies for

common audio sampling rates.

Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock

source with low phase jitter and noise.

Table 1. System Clock Frequency for Common Audio Sampling Frequencies

SAMPLING FREQUENCY, LRCK

SYSTEM CLOCK FREQUENCY, SCKI (MHz)

128 fS

192 fS

256 fS

384 fS

48 kHz

6.144

9.216

12.288

18.432

44.1 kHz

5.6448

8.4672

11.2896

16.9344

32 kHz

4.096

6.144

8.192

12.288

24 kHz

3.072

4.608

6.144

9.216

22.05 kHz

2.8224

4.2336

5.6448

8.4672

16 kHz

2.048

3.072

4.096

6.144

12 kHz

1.536

2.304

3.072

4.608

11.025 kHz

1.4112

2.1168

2.8224

4.2336

8 kHz

1.024

1.536

2.048

3.072

t(SCKH)

System Clock

Pulse Cycle Time†

SCKI

t(SCKL)

0.7 VCC

0.3 VCC

† 1/(128fS), 1/(192fS), 1/(256fS), and 1/(384fS)

PARAMETERS

SYMBOL

MIN

UNIT

System clock pulse width high

t(SCKH)

7

ns

System clock pulse width low

t(SCKL)

7

ns

Figure 18. System Clock Timing