CDCV304

140-MHz PCI-X CLOCK BUFFER

SCAS643B – SEPTEMBER 2000 REVISED JULY 2002

3

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

Input voltage

VDD = 3 V,

II = –18 mA

–1.2

V

VDD = min to max, IOH = –1 mA

VDD–0.2

VOH

High-level output voltage

VDD = 3 V,

IOH = –24 mA

2

V

VDD = 3 V,

IOH = –12 mA

2.4

VDD = min to max, IOL = 1 mA

0.2

VOL

Low-level output voltage

VDD = 3 V,

IOL = 24 mA

0.8

V

VDD = 3 V,

IOL = 12 mA

0.55

IOH

High level output current

VDD = 3 V,

VO = 1 V

–50

mA

IOH

High-level output current

VDD = 3.3 V,

VO = 1.65 V

–55

mA

IOL

Low level output current

VDD = 3 V,

VO = 2 V

60

mA

IOL

Low-level output current

VDD = 3.3 V,

VO = 1.65 V

70

mA

II

Input current

VI = VO or VDD

±5

µA

IDD

Dynamic current, See Figure 5

f = 67 MHz

37

mA

Ci

Input capacitance

VDD = 3.3 V,

VI = 0 V or VDD

3

pF

Co

Output capacitance

VDD = 3.3 V,

VI = 0 V or VDD

3.2

pF

† All typical values are at respective nominal VDD and 25°C.

switching characteristics over recommended ranges of supply voltage and operating free-air

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH

High-to-low propagation delay

See Figures 1 and 2

1.8

2.5

3

ns

tPHL

Low-to-high propagation delay

See Figures 1 and 2

1.8

2.4

3

ns

tsk(o)

Output skew (see Note 4)

50

100

ps

tsk(p)

Pulse skew

VIH = VDD, VIL = 0 V

150

ps

tsk(pr)

Process skew

0.2

0.3

ns

tsk(pp)

Part-to-part skew

0.25

0.4

ns

Thi h

CLK high time See Figure 4

66 MHz

6

ns

Thigh

CLK high time, See Figure 4

140 MHz

3

ns

Tl

CLK low time See Figure 4

66 MHz

6

ns

Tlow

CLK low time, See Figure 4

140 MHz

3

ns

tr

Output rise slew rate‡

0.2VDD to 0.6VDD

1.5

2.7

4

V/ns

tf

Output fall slew rate‡

0.6VDD to 0.2VDD

1.5

2.7

4

V/ns

† All typical values are at respective nominal VDD.

‡ This symbol is according to PCI-X terminology.

NOTE 4: The tsk(o) specification is only valid for equal loading of all outputs.