N/C

Bal/Comp1

-IN

+IN

N/C

Comp2

V+

OUT

1

10

2

9

3

8

4

7

V-

Bal/Comp3

5

6

LM118QML

SNOSAJ3A – JULY 2005 – REVISED MARCH 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Connection Diagram

Figure 1. CDIP Package

Figure 2. TO-99

Top View

Top View

See Package Number J0014A

See Package Number LMC

Pin connections shown on schematic diagram and typical

applications are for TO package.

Figure 3. CDIP Package

Figure 4. CLGA Package

Top View

Top View

See Package Number NAB0008A

See NS Package Number NAC0010A

2

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