TPS70802 datasheet(21/29 Pages) TI

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VOUT2

VIN1

VIN2

EN1

EN2

VOUT1

VSENSE1

PG1

RESET

PG2

VSENSE2

VOUT2

VIN

VOUT1

PG2

0.1

µF

RESET

µF

0.1

µF

EN1

2 V

0.7 V

TPS708xxPWP

(Fixed Output Option)

>2 V

<0.7 V

EN2

250 k

>2 V

<0.7 V

TPS70845, TPS70848, TPS70851, TPS70858, TPS70802

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

SLVS301B – JUNE 2000 – REVISED OCTOBER 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

application conditions not shown in block diagram:

VIN1 and VIN2 are tied to the same fixed input

voltage greater than VUVLO. MR is initially logic

high but is eventually toggled.

explanation of timing diagrams:

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 and PG2 are at logic

low. Since VIN1 is greater than VUVLO and MR is

at logic high, RESET is also at logic high. When

EN2 is taken to logic low, VOUT2 turns on. Later,

when EN1 is taken to logic low, VOUT1 turns on.

When VOUT2 reaches 95% of its regulated output

voltage, PG2 goes to logic high. When VOUT1

reaches 95% of its regulated output voltage, PG1

goes to logic high. When MR is taken to logic low,

RESET is taken low. When MR returns to logic

high, RESET returns to logic high after a 120 ms

delay.

95%

EN2

VOUT2

VOUT1

PG2

PG1

RESET

95%

120ms

EN1

NOTES: A. t1 – Time at which VIN is greater than VUVLO and MR is logic high.

B. The timing diagrams are not drawn to scale.

Figure 35. Timing When MR Is Toggled

TPS70802 Datasheet(PDF) 21 Page - Texas Instruments

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