MAX783 datasheet(13/28 Pages) MAXIM

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Triple-Output Power-Supply Controller

for Notebook Computers

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continuously receiving current from the inductor. This

minimizes output ripple and maximizes inductor use,

allowing very small physical and electrical sizes. Output

ripple is primarily a function of the filter capacitor effec-

tive series resistance (ESR) and is typically under 50mV

(see the

Design Procedure section). Output ripple is

worst at light load and maximum input voltage.

Idle Mode

Under light loads (<25% of full load), efficiency is fur-

ther enhanced by turning the drive voltage on and off

for only a single clock period, skipping most of the

clock pulses entirely. Asynchronous switching, seen as

“ghosting” on an oscilloscope, is thus a normal operating

condition whenever the load current is less than

approximately 25% of full load.

At certain input voltage and load conditions, a transition

region exists where the controller can pass back and

forth from idle-mode to PWM mode. In this situation,

short bursts of pulses occur that make the current

waveform look erratic, but do not materially affect the

output ripple. Efficiency remains high.

Current Limiting

The voltage between CS3 (CS5) and FB3 (FB5) is contin-

uously monitored. An external, low-value shunt resistor

is connected between these pins, in series with the

inductor, allowing the inductor current to be continuously

measured throughout the switching cycle. Whenever

this voltage exceeds 100mV, the drive voltage to the

external high-side MOSFET is cut off. This protects the

MOSFET, the load, and the battery in case of short cir-

cuits or temporary load surges. The current-limiting

resistor R1 (R2) is typically 25m

Ω (20mΩ) for a 3A load

current.

Oscillator Frequency; SYNC Input

The SYNC input controls the oscillator frequency.

Connecting SYNC to GND or to VL selects 200kHz opera-

tion; connecting to REF selects 300kHz operation. SYNC

can also be driven with an external 240kHz to 350kHz

CMOS/TTL source to synchronize the internal oscillator.

300kHz operation is used to minimize the inductor and

filter capacitor sizes, but 200kHz may be necessary for

low input voltages (see

Low-Voltage Operation).

High-Side Supply (VDD)

The 15V VDD supply is obtained from the rectified and

filtered secondary of transformer L2. VDD is enabled

whenever the +3.3V supply is on (ON3 = high). The

primary and secondary of L2 are connected so that,

during the flyback (discharge) portion of each cycle,

energy stored in the core is transferred into the +3.3V

load through the primary and into VDD through the sec-

ondary, as determined by the turns ratio. The sec-

ondary voltage is added to the +3.3V to make VDD.

See the

Typical Operating Characteristics for the VDD

supply’s load capability.

Unlike other coupled-inductor flyback converters, the

VDD voltage is regulated regardless of the loading on

the +3.3V output. (Most coupled-inductor converters

can only support the auxiliary output when the main

output is loaded.) When the +3.3V supply is lightly

loaded, the circuit achieves good control of VDD by

pulsing the MOSFET normally used as the synchronous

rectifier. This draws energy from the +3.3V supply’s

output capacitor and uses the transformer in a forward-

converter mode (i.e., the +15V output takes energy out

of the secondary when current is flowing in the prima-

ry). These forward-converter pulses are interspersed

with normal synchronous-rectifier pulses, and they only

occur at light loads on the +3.3V rail.

The transformer secondary’s rectified and filtered out-

put is only roughly regulated, and may be between 13V

and 19V. It is brought back into VDD, which is also the

feedback input, and used as the source for the PCMCIA

VPP regulators. It can also be used as the VH power

supply for the comparators or any external MOSFET

drivers.

When the input voltage is above 12V, or when the

+3.3V supply is heavily loaded and VDD is lightly

loaded, L2’s interwinding capacitance and leakage

inductance can produce voltages above that calculat-

ed from the turns ratio. A 2.5mA shunt regulator limits

VDD to 19V. If the battery voltage can rise above 12V,

VDD must either be externally clamped with an 18V

zener diode, or there must be a 1mA minimum load on

VDD (or VPPA/VPPB).

Clock-frequency noise on the VDD rail of up to 3VP-P is

a facet of normal operation, and can be reduced by

adding more output capacitance.

PCMCIA-Compatible,

Programmable VPP Supplies

Two independent linear regulators furnish PCMCIA VPP

supplies. The VPPA and VPPB outputs can be pro-

grammed to deliver 0V, 3.3V, 5V, or 12V. The 0V out-

put mode has a 250

Ω pull-down to discharge external

filter capacitors and ensure that flash EPROMs cannot

be accidentally programmed. These linear regulators

draw their power from the high-side supply (VDD), and

each can furnish up to 60mA. Bypass VPPA and VPPB

to GND with at least 1µF, with the bypass capacitors

less than 20mm from the VPP pins.

The outputs are programmed with DA0, DA1, DB0 and

DB1, as shown in Table 2.

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