12

nSD

9

RTN

13

SD

2.5V

-

+

11

nPGOOD

pgood

50 PA

LM5073

External Bias

LED to indicate

"Powered from PoE"

rear aux

LM5073

www.ti.com

SNVS490C – MARCH 2007 – REVISED APRIL 2013

Figure 13. "Powered-from-PoE" Indictor, Power Good Delay Timer and Shut Down Control Outputs

The nPGOOD pin can also be used to implement a delay timer by adding a capacitor from the nPGOOD pin to

the RTN pin. This delay timer will prevent the interruption of the DC-DC converter’s operation in the event of an

intermittent loss of power good status. This can be caused by PoE line voltage transients that may occur when

switching between normal PoE power and a backup supply (e.g. a battery or UPS). Such a condition will create a

new “hot swap” event if the backup supply voltage is greater than the PoE supply. Since the hot swap MOSFET

will likely limit current during such a sudden input voltage change, the nPGOOD pin will momentarily switch to

the high state. A capacitor on this pin will delay the transition of the nPGOOD pin to provide continuous operation

of the DC-DC converter during such transients. The power good filter delay time and capacitor value can be

selected with the following equation:

(4)

operation will depend on the amplitude of the transient, the DC current limit, the load, and the total amount of

input capacitance. The nPGOOD delay timer will not ensure continuous operation if the hot swap MOSFET is in

current limit for an extended period, causing a thermal limit condition. This will result in a complete shutdown of

the DC-DC converter, though no elements in the system will be permanently damaged and normal operation will

resume momentarily.

The power good status also affects the default DC current limit. Should the sensed drain to source voltage of the

hot swap MOSFET (from RTN to VEE) exceed 2.5V, the LM5073 will increase the DC current limit from the

default 440 mA to 800 mA (High DCCL). This higher current limit will speed recovery from an input voltage

downward step, allowing continued operation of the PD. This higher current limit will remain in effect until one of

converter will be disabled, (ii) the increased power dissipation in the hot swap MOSFET causes a thermal limit

condition as previously discussed, or (iii) the hot swap MOSFET drain to source voltage falls below 1.5V to re-

the DC Current Limit section), then the DC current limit will remain at the programmed level even when the

power good status is lost.

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