XR28V384 datasheet(21/42 Pages) EXAR

21 / 42 page

XR28V384

REV. 1.0.0

3.3V QUAD LPC UART WITH 128-BYTE FIFO

2.1.1

Global Control Registers

2.1.1.1

Software Reset Register

Software Reset resets the Device Configuration registers to their factory defaults. Strapping pins from

Table 1

are not sampled during a software reset.

Bit [0]: Software reset

Logic 0 = Disable software reset (default).

Logic 1 = Enable software reset. After the software reset, this bit will turn to ’0’ automatically.

Bits [7:1]: Reserved

2.1.1.2

Logic Device Number Register - Read/Write

This register selects device configuration register set among the 4 channel UARTs and the watchdog timer.

Bits [7:0]: Select different device configuration register set.

0x00 = Select UART A device configuration register (default).

0x01 = Select UART B device configuration register.

0x02 = Select UART C device configuration register.

0x03 = Select UART D device configuration register.

0x08 = Select Watchdog Timer device configuration register.

2.1.1.3

Device ID MSB/LSB Register - Read only

DEV_ID_M (0x20): This register provides upper byte device ID for XR28V384. The default value is 0x03.

DEV_ID_L (0x21): This register provides lower byte device ID for XR28V384. The default value is 0x84.

2.1.1.4

Vendor ID MSB/LSB Register - Read only

VID_M (0x23): This register value provides upper byte of Exar’s Vendor ID. The default value is 0x13.

VID_L (0x24): This register value provides lower byte of Exar’s Vendor ID. The default value is 0xA8.

2.1.1.5

Clock Select Register - Read/Write

This register selects the clock frequency.

Bit [0]: Clock select

Logic 0 = The CLKIN is 24 MHz (default).

Logic 1 = The CLKIN is 48 MHz.

Bits [7:1]: Reserved

2.1.1.6

Watchdog Timer Control Register - Read/Write

This register controls the watchdog timer.

Bit [0]: Assert a low pulse from WDTOUT# pin

Logic 0 = Watchdog timer (WDT) will assert a low pulse from WDTOUT# pin (default).

Logic 1 = Watchdog timer (WDT) will not assert a low pulse from WDTOUT# pin, but the timeout status will

be set.

Bit [1]: Restart timer

Logic 0 = Read watchdog timer (WDT) will restart the timer (default).

Logic 1 = Read watchdog timer (WDT) will not restart the timer.

XR28V384 Datasheet(PDF) 21 Page - Exar Corporation

XR28V384 Datasheet(HTML) 21 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL