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ADVANCE INFORMATION

LM9630 100 x 128, 580 fps Ultra Sensitive Monochrome CMOS Image Sensor

General Description

The LM9630 is a high performance, low power, CMOS Active

Pixel Image Sensor capable of capturing monochrome images

at 580 frames per second.

In addition to the active pixel array, an on-chip 8 bit A/D conver-

tor, fixed pattern noise elimination circuits and a video gain

amplifier are provided.

The integrated programmable timing and control circuit allows

the user maximum flexibility in adjusting integration time and

frame rate. Furthermore, a fast read out circuit is provided allow-

ing a full frame to read out on a single 8-bit digital data bus in

less than 2ms.

The sensor utilizes a patented pixel design that incorporates an

integrated electronic shutter. This together with its ultra high sen-

sitivity makes the LM9630 an ideal choice for low light imaging

applications or applications where images of fast moving objects

need to be captured with minimum motion blur.

Applications

f

High Speed Motion Detection

f

IR Imaging

f

Low Light Imaging Applications

Features

f

Electronic shutter with global reset & pixel exposure.

f

Programmable analog video gain.

f

Integrated 8 bit analog to digital conversion.

f

Programmable integration time.

f

Programmable frame rate.

f

Master and slave mode of operation

f

On chip black level compensation.

f

Power down and low power modes.

f

f

10 bit digital video port (8 data, vertical & horizontal sync).

f

Power on reset with hardware and software override.

Key Specifications

Array Format

Total

Active

128H x 101V

118H x 96V

Effective Image Area

Total

Active

2.56 mm x 2.00 mm

2.36 mm x 1.92 mm

Optical Format

1/5”

Pixel Size

20

µm x 20µm

Video Outputs

8 Bit Digital

Frame Rate

580 frames per second

Dynamic Range

48 dB

Electronic Shutter

Global Reset

FPN

0.5%

PRMU

1.3%

Sensitivity

22 Volt/lux.s

Fill Factor

47%

Package

32 CLCC

Single Supply

3.3V +/- 10%

Power Consumption

110 mW

Operating Temp

Chip Block Diagram

Column CDS

APS Array

Shift

Register

8 Bit A/D

AMP

d[7:0]

hsync

vsync

Master Timer

Register

Gain

POR

Digital

Image Data

Framer

Register Bank

Serial I/F

sda

sclk

Clock Gen

Reset Gen

mclk

reset

Register

Offset

+

May 2002