Figure 1. Operational Amplifier Protection

Figure 2. Sample and Hold Circuit

Typical Sample and Hold circuit with clipping. ID100 diodes reduce offset

voltages fed capacitively from the ID100 switch gate.

FIGURE 1

2N4117A

R

2N4393

-V

+V

V

OUT

D2

D1

C

ID100

CONTROL

SIGNAL

e

in

+V

FIGURE 2

-15V

+15V

OP-27

D1

D2

D3

D4

+

-

ID100

TO-78

0.335

0.370

0.305

0.335

0.016

0.019

0.165

0.185

0.040

MAX.

DIM. A

0.016

0.021

DIM. B

MIN. 0.500

0.200

0.100

0.100

0.028

0.034

45°

1

2 3

5

6

7

0.029

0.045

SEATING

PLANE

TO-71

Six Lead

0.230

0.209

DIA.

DIA.

0.195

0.175

0.030

MAX.

0.500 MIN.

0.150

0.115

0.019

0.016

DIA.

6 LEADS

3

2

1

5

6

0.046

0.036

45°

0.048

0.028

0.100

0.050

7

1.

Absolute maximum ratings are limiting values above which serviceability may be impaired.

2.

Design reference only, not 100% tested.

3.

Pins 3 & 5 on ID100 and ID101 must not be connected, in any fashion or manner, to any circuit or node.

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n or