LMP93601 datasheet(21/44 Pages) TI1

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LMP93601

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SNAS633A – MARCH 2014 – REVISED SEPTEMBER 2014

Table 5. Wake Up Time From Low Power Modes (continued)

Mode

Registers

Power

Wake Up Time

Programmable via

Standby

Maintained

~175 µA

~100 µs to go to

SPI

conversion mode

Conversion

Maintained

1.1 mA

n/a

SPI

8.3.16 Power-On Sequence and Reset (POR) Function

An internal power on reset is generated after both the internal LDO (to supply the internal digital) and IOVDD

reach valid values. The internal LDO will reach stable values only after the AVDD has reached at least 2.7 V.

The device should be powered up with AVDD enabled and stabilized first, then the IOVDD. This allows the

device to start in the default power up state and ensures that the internal power on reset is generated after both

the internal LDO (to supply the internal digital) and IOVDD reach valid values. The internal LDO will reach stable

values only after the AVDD has reached at least 2.7 V for 1 ms. Alternatively, AVDD and IOVDD can be

connected together, but this can result in an erroneous brown-out condition being reported when the ramp time

of the supplies is slower than 0.1 V/ms. For example, if the AVDD = IOVDD are linearly ramped from 0 to 3.3 V

in longer than 330 µs, the brown could possibly trigger and be logged in the status register and the first

conversion result could read ‘7FFF’. To avoid this erroneous brown-out report, three alternative solutions are

available:

a. After the supplies are stable, reset the part (either with the RSTB pin or with a soft reset via SPI). After this

reset, the part can be programmed and used as intended.

b. Or, after the supplies are stable, program the part as desired, but before initiating the first conversion, read

back the status register(s) of the enabled channel(s) to clear the erroneous brown-out status.

c. Or, wait supplying the XCLK to the part until after the supplies are stable

8.3.17 Brown-Out Detection Function

A brown-out detection circuit monitors the AVDD. It triggers an alarm only when AVDD falls below ~2.55 V and

stays below 2.55 V for more than 16 fxclk cycles. The brown-out detection has a hysteresis of ~65 mV. The

alarm will result in “0x7FFF” data and the appropriate channel status register(s) can be read to decode the alarm.

The brown-out error function can be masked via SPI with the “alarm mask” register.

8.3.18 Reset Function

The device can be reset to the default (Standby) state via the SPI or taking the RSTB pin low. The reaction time

from the reset (either via SPI or RSTB pin) to the device getting to Standby mode is on the order of 100 µs. See

Table 6

8.4 Device Functional Modes

8.4.1 Single-Shot Mode

In Single Shot mode each conversion is triggered by a Start Trigger from the microcontroller unit (MCU) to the

LMP93601 by pulsing the SYNC pin or via a start SPI command (SYNC is recommended for exact timing

control). After the LOCK bit is set, the external µC should wait 3 XCLK cycles before it sends a start trigger. This

is to allow the internal synchronizer enough time to synchronize the SPI write of the LOCK bit into the XCLK

domain. This assumes the analog has already settled (otherwise, allow ~100 µs to go from standby to conversion

mode).

The SYNC has typical setup/hold time of 20 ns with respect to XCLK, as shown in Figure 19.

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