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P89LPC921 Datasheet(PDF) 36 Page - NXP Semiconductors |
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P89LPC921 Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 45 page  Philips Semiconductors P89LPC920/921/922 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 06 — 21 November 2003 36 of 45 9397 750 12285 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. [2] The IDD, IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and Watchdog timer. [3] See Table 7 “Limiting values” on page 34 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. [4] Pin capacitance is characterized but not tested. [5] Measured with port in quasi-bidirectional mode. [6] Measured with port in high-impedance mode. [7] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open-drain pins. [8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest when VIN is approximately 2 V. 11. Dynamic characteristics [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. Table 9: AC characteristics Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fOSC =12MHz Unit Min Max Min Max fRCOSC internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to ±1% at Tamb =25 °C 7.189 7.557 7.189 7.557 MHz fWDOSC internal Watchdog oscillator frequency (nominal f = 400 kHz) 280 480 280 480 kHz fOCS oscillator frequency 0 12 - - MHz tCLCL clock cycle see Figure 13 83 - - - ns fCLKP CLKLP active frequency 0 8 - - MHz Glitch filter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock tCHCX HIGH time see Figure 13 33 tCLCL − tCLCX 33 - ns tCLCX LOW time see Figure 13 33 tCLCL − tCHCX 33 - ns tCLCH rise time see Figure 13 -8 - 8 ns tCHCL fall time see Figure 13 -8 - 8 ns Shift register (UART mode 0) tXLXL serial port clock cycle time 16 tCLCL - 1333 - ns tQVXH output data set-up to clock rising edge 13 tCLCL - 1083 - ns tXHQX output data hold after clock rising edge -tCLCL + 20 - 103 ns tXHDX input data hold after clock rising edge - 0 - 0 ns tDVXH input data valid to clock rising edge 150 - 150 - ns |
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