TL16C552

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS102B − DECEMBER 1990 − REVISED MARCH 1996

16

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PRINCIPLES OF OPERATION

Three types of information are stored in the internal registers used in the ACE: control, status, and data.

Mnemonic abbreviations are shown in the Table 1 for the registers.

Table 1. Internal Register Types With Mnemonics

CONTROL

MNEMONIC

STATUS

MNEMONIC

DATA

MNEMONIC

Line control register

LCR

Line status register

LSR

Receiver buffer register

RBR

FIFO control register

FCR

Modem status register

MSR

Transmitter holding register

THR

Modem control register

MCR

Divisor latch LSB

DLL

Divisor latch MSB

DLM

Interrupt enable register

IER

The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register

(bit 7) to select the register to be written to or read from (see Table 2).

DLAB

A2

A1

A0

MNEMONIC

REGISTER

L

L

L

L

RBR

Receiver buffer register (read only)

L

L

L

L

THR

Transmitter holding register (write only)

L

L

L

H

IER

Interrupt enable register

X

L

H

L

IIR

Interrupt identification register (read only)

X

L

H

L

FCR

FIFO control register (write only)

X

L

H

H

LCR

Line control register

X

H

L

L

MCR

Modem control register

X

H

L

H

LSR

Line status register

X

H

H

L

MSR

Modem status register

X

H

H

H

SCR

Scratch register

H

L

L

L

DLL

Divisor latch (LSB)

H

L

L

H

DLM

Divisor latch (MSB)

† X = irrelevant, L = low level, H = high level

‡ The serial channel is accessed when either CS0 or CS1 is low.

Individual bits within the registers are referred to by the register mnemonic and the bit number in parenthesis.

As an example, LCR7 refers to line control register bit 7.

The transmitter buffer register and receiver buffer register are data registers that hold from five to eight bits of

data. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always

the first serial data bit received and transmitted. The ACE data registers are double buffered so that read and

write operations may be performed when the ACE is performing the parallel-to-serial or serial-to-parallel

conversion.