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DSC2011

Page 3

MK-Q-B-P-D-12042602-2

DSC2011

Low-Jitter Configurable Dual CMOS Oscillator

Output Clock Frequencies

Table 2 lists the standard frequency configurations and the associated ordering information to be

used in conjunction with the ordering code above. Customer defined combinations are available.

Table 2. Pre-programmed pin-selectable output frequency combinations

Ordering

Info

Freq

(MHz)

Freq Select Bits [FS2, FS1, FS0] – Default is [111]

000

001

010

011

100

101

110

111

E0001

27

25

50

54

48

24

24

24

24

125

125

27

24

50

54

27

E0002

106.25

100

125

100

156.25

156.25

125

156.25

25

100

50

50

25

125

25

156.25

E0004

24

75

125

48

74.25

148.5

50

25

24

75

125

48

74.25

148.5

50

25

E0005

25

0*

0*

0*

0*

0*

0*

25

25

0*

0*

0*

0*

0*

0*

25

E0006

27

74.175

74.25

148.35

148.5

0*

0*

0*

13.5

37.0875 37.125 74.175

74.25

0*

0*

0*

E0007

24

0*

0*

0*

0*

0*

0*

0*

40

0*

0*

0*

0*

0*

0*

0*

E0008

40

40

40

20

40

20

40

20

200

128

120

120

100

100

80

80

EXXXX

Contact factory for additional configurations.

Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and

the device will output the associated frequency highlighted in Bold.

0* – denotes invalid selection, output frequency is not specified.