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LP3921 Datasheet(PDF) 16 Page - Texas Instruments |
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LP3921 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 41 page  LDO2 - 7 PS_HOLD LDO1 If PS_HOLD is low 35 ms after initially going low, then LDO2-7 are shutdown LDO1 is shutdown 40 Ps after other LDO's are shutdown 35 ms 40 Ps RESET CHG_IN HF_PWR PS_HOLD LDO1 LDO2 320 ms 87% 87% Reg PS_HOLD needs to be asserted within 1200 ms after HF_PWR, or CHG_IN rising edge has been detected. If charger is connected (CHG_IN) or HF_PWR is applied, then both events are filtered for 320 ms before enabling LDO1 60 ms 1.2s If no enabling signal is high on the rising edge of PS_HOLD, shutdown will occur. RESET 200 Ps Either HF_PWR or CHG_IN will enable LDO1 LP3921 SNVS580A – AUGUST 2008 – REVISED MAY 2013 www.ti.com Figure 4. LP3921 Power On Behavior (Failed PS_Hold) Figure 5. LP3921 Normal Shutdown Behavior LP3921 Serial Port Communication Slave Address Code 7h’7E 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LP3921 |
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