CS5516-AS datasheet(25/41 Pages) CIRRUS

25 / 41 page

The digital filter computes a new output data

word every 81,920 XIN clock cycles. If the in-

put experiences a large change in amplitude, the

PGA gain is changed, or the DAC calibration

registers are changed, it may take up to six filter

cycles (81,920 X 6 clock cycles) for the filter to

compute an output word which is fully settled to

the input signal.

Output Coding

The CS5516/20 converters output data in binary

format when operating in unipolar mode and in

two’s complement when operating in bipolar

mode. Table 5 illustrates the output coding for

the converters. Note that when reading conver-

sion data from the converter the data word is

output MSB or sign bit first. Falling edges on

SCLK advance the data word to the next lower

bit.

The output conversion words from both the

CS5516 and the CS5520 are 24 bits long. The

CS5516 has 16 data bits followed by 8 flag bits

(all identical). The CS5520 has 20 data bits fol-

lowed by 4 flag bits (all identical). To read the

conversion data, including the error flag infor-

mation will require at least 17 SCLKs for the

CS5516 and at least 21 SCLKs for the CS5520.

Under normal operating conditions, the flag bits

will be zeroes. The flag bits will be set to all

ones whenever an overrange condition exists.

Under large overrange conditions where the in-

put signal exceeds the nominal full scale input

by approximately two times (for example:

50 mV input when the nominal full scale input

is set-up for 25 mV), the converter may be un-

able to compute a proper output code. In this

condition flag bits will be set to all 1s but the

conversion data may be a value other than full

scale plus or minus.

After the converter is first powered-up, a RST is

issued, or the device comes out of the SLEEP

mode, the first conversion data read may

erroneously have its error flag bits set to "1".

Synchronizing Multiple Converters

Multiple converters can be made to output their

conversion words at the same time if they are

operated from the same clock signal at XIN. To

synchronize multiple converters requires that

they all have their RF bit of the configuration

The filters will be allowed to start convolutions

after the falling edge of the 24th SCLK used to

write the RF bit to the configuration register.

Unipolar Input

Voltage

Offset

Binary

Bipolar Input

Voltage

Two’s

Complement

Unipolar Input

Voltage

Offset

Binary

Bipolar Input

Voltage

Two’s

Complement

>(VFS-1.5 LSB) FFFF

>(VFS-1.5 LSB)

7FFF

>(VFS-1.5 LSB) FFFFF >(VFS-1.5 LSB)

7FFFF

VFS-1.5 LSB

FFFF

-----

FFFF

VFS-1.5 LSB

7FFF

-----

7FFE

VFS-1.5 LSB

FFFFF

-----

FFFFE

VFS-1.5 LSB

7FFFF

-----

7FFFE

VFS/2-0.5 LSB

8000

-----

7FFF

-0.5 LSB

0000

-----

FFFF

VFS/2-0.5 LSB

80000

-----

7FFFF

-0.5 LSB

00000

-----

FFFFF

+0.5 LSB

0001

-----

0000

-VFS+0.5 LSB

8001

-----

8000

+0.5 LSB

00001

-----

00000

-VFS+0.5 LSB

80001

-----

80000

<(+0.5 LSB)

0000

<(-VFS+0.5 LSB)

8000

<(+0.5 LSB)

00000 <(-VFS+0.5 LSB)

80000

CS5516 Output Coding

CS5520 Output Coding

Note: VFS in the table equals the full scale voltage between +VREF/(G x 25) and ground for unipolar mode; and

between

±VREF/(G x 25) for bipolar mode. The signal input to the A/D section of the converter has been

amplified by the instrumentation amplifier (x25) and the PGA gain, G (1, 2, 4, or 8). See text about error

flags under overrange conditions.

Table 5. Output Coding for the CS5516/20 Converters.

CS5516, CS5520

DS74F1

DS74F2

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