®

LOG100

3

LOG100JP

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

POWER SUPPLY REQUIREMENTS

Rated Voltage

±15

VDC

Operating Range

Derated Performance

±12

±18

VDC

Quiescent Current

±7

±9mA

AMBIENT TEMPERATURE RANGE

Specification

0

+70

°C

Operating Range

Derated Performance

–25

+85

°C

Storage

–40

+85

°C

ELECTRICAL

T

NOTES: (1) Log Conformity Error is the peak deviation from the best-fit straight line of the V

output. (2) May be trimmed to other values. See Applications section. (3) The worst-case Total Error for any ratio of I

I

amplifier’s committed configuration. (6) 3dB and transient response are a function of both the compensation capacitor and the level of input current. See Typical

Performance Curves.

PIN CONFIGURATION

K, V/DECADE

CONNECTIONS

5

5 to 7

3

4 to 7

1.9

4 and 5 to 7

1

3 to 7

0.85

3 and 5 to 7

0.77

3 and 4 to 7

0.68

3 and 4 and 5 to 7

SCALE FACTOR PIN CONNECTIONS

ABSOLUTE MAXIMUM RATINGS

Supply ................................................................................................

±18V

Internal Power Dissipation .............................................................. 600mV

Input Current ..................................................................................... 10mA

Input Voltage Range ..........................................................................

±18V

Storage Temperature Range ........................................... –40

°C to +85°C

Lead Temperature (soldering, 10s) ............................................... +300

°C

Output Short-circuit Duration .................................. Continuous to ground

Junction Temperature ...................................................................... 175

°C

FREQUENCY COMPENSATION

1

C

C

14

9

6

7

10

543

LOG100

Bottom View

NC = No Connection

I

Scale Factor Trim

K = 1

K = 3

K = 5

+V

CC

Output

I

NC

NC

NC

Common

–V

CC

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

ORDERING INFORMATION

SPECIFIED

TEMPERATURE

MODEL

PACKAGE

RANGE

LOG100JP

14-Pin Hermetic Ceramic DIP

0

°C to +70°C

ELECTROSTATIC

DISCHARGE SENSITIVITY

Any integral circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

PACKAGE INFORMATION

PACKAGE DRAWING

MODEL

PACKAGE

LOG100JP

14-Pin Hermetic Ceramic DIP

NOTES: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book. (2) During 1994, the package

was changed from plastic to hermetic ceramic. Pinout, model number, and

specifications remained unchanged. The metal lid of the new package is

internally connected to common, pin 10.