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TLC32044MFKB Datasheet(PDF) 26 Page - Texas Instruments |
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TLC32044MFKB Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 39 page ![]() TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I VOICE-BAND ANALOG INTERFACE CIRCUITS SLAS017F − MARCH 1988 − REVISED MAY 1995 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC− = −5 V, VDD = 5 V noise (measurement includes low-pass and bandpass switched-capacitor filters) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT TLC32044C, E, I 550 µV rms TLC32044M With sin x / x correction 575 µV rms TLC32045C, I With sin x / x correction 600 µV rms Transmit noise TLC32044C, E, I DX input = 00 00 00 00 00 00 00, 325 425 µV rms Transmit noise TLC32044M DX input = 00 00 00 00 00 00 00, constant input code 325 450 µV rms TLC32045C, I Without sin x / x correction constant input code 450 µV rms TLC32044C, E, I Without sin x / x correction 18 dBrncO TLC32045C, I 24 dBrncO TLC32044C, E, I, M 300 500 µV rms Receive noise TLC32045C, I Inputs grounded, gain = 1 530 µV rms Receive noise (see Note 10) TLC32044C, E, I, M Inputs grounded, gain = 1 18 dBrncO (see Note 10) TLC32045C, I 24 dBrncO † All typical values are at TA = 25°C. NOTE 10: The noise is computed by statistically evaluating the digital output of the A/D converter. timing requirements serial port recommended input signals MIN MAX UNIT tc(MCLK) Master clock cycle time 95 ns tc(MCLK) Master clock cycle time, TLC32044M 100 192 ns tr(MCLK) Master clock rise time 10 ns tf(MCLK) Master clock fall time 10 ns Master clock duty cycle 25% 75% Master clock duty cycle, TLC32044M 42% 58% RESET pulse duration (see Note 11) 800 ns tsu(DX) DX setup time before SCLK ↓ 20 ns tsu(DX) DX setup time before SCLK ↓, TLC32044M 28 ns th(DX) DX hold time after SCLK ↓ tc(SCLK)/4 ns NOTE 11: RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached their recommended values. |
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