TPS73601DBVR datasheet(12/27 Pages) TI

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Board Layout Recommendation to Improve

Transient Response

Internal Current Limit

Shutdown

(Fixed Voltage Version)

dV dt

OUT

80kW ø RLOAD

(4)

Dropout Voltage

(Adjustable Voltage Version)

dV dt

OUT

80kW ø (R1 ) R2) ø RLOAD

(5)

TPS736xx

SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005

This noise reduction effect is shown as RMS Noise

For large step changes in load current, the TPS736xx

Voltage vs CNR in the Typical Characteristics section.

requires a larger voltage drop from VIN to VOUT to

avoid degraded transient response. The boundary of

The TPS73601 adjustable version does not have the

this transient dropout region is approximately twice

noise-reduction pin available. However, connecting a

the dc dropout. Values of VIN - VOUT above this line

feedback capacitor, CFB , from the output to the FB

insure normal transient response.

pin will reduce output noise and improve load transi-

ent performance.

Operating in the transient dropout region can cause

an increase in recovery time. The time required to

The TPS736xx uses an internal charge pump to

recover from a load transient is a function of the

develop an internal supply voltage sufficient to drive

magnitude of the change in load current rate, the rate

the gate of the NMOS pass element above VOUT. The

of change in load current, and the available head-

charge pump generates ~250µV of switching noise at

room (VIN to VOUT voltage drop). Under worst-case

~4MHz; however, charge-pump noise contribution is

conditions [full-scale instantaneous load change with

negligible at the output of the regulator for most

(VIN - VOUT) close to dc dropout levels], the TPS736xx

values of IOUT and COUT.

can take a couple of hundred microseconds to return

to the specified regulation accuracy.

PSRR and Noise Performance

To improve ac performance such as PSRR, output

The low open-loop output impedance provided by the

noise, and transient response, it is recommended that

NMOS pass element in a voltage follower configur-

the board be designed with separate ground planes

ation allows operation without an output capacitor for

for VIN and VOUT, with each ground plane connected

many applications. As with any regulator, the addition

only at the GND pin of the device. In addition, the

of a capacitor (nominal value 1µF) from the output pin

ground connection for the bypass capacitor should

to ground will reduce undershoot magnitude but

connect directly to the GND pin of the device.

increase duration. In the adjustable version, the

addition of a capacitor, CFB, from the output to the

adjust pin will also improve the transient response.

The TPS736xx internal current limit helps protect the

The TPS736xx does not have active pull-down when

regulator during fault conditions. Foldback helps to

the output is over-voltage. This allows applications

protect the regulator from damage during output

that connect higher voltage sources, such as alter-

short-circuit conditions by reducing current limit when

nate power supplies, to the output. This also results

VOUT drops below 0.5V. See Figure 11 in the Typical

in an output overshoot of several percent if load

Characteristics section for a graph of IOUT vs VOUT.

current quickly drops to zero when a capacitor is

connected to the output. The duration of overshoot

can be reduced by adding a load resistor. The

overshoot decays at a rate determined by output

The Enable pin is active high and is compatible with

capacitor COUT and the internal/external load resist-

standard TTL-CMOS levels. VEN below 0.5V (max)

ance. The rate of decay is given by:

turns the regulator off and drops the ground pin

current to approximately 10nA. When shutdown capa-

bility is not required, the Enable pin can be connected

to VIN. When a pull-up resistor is used, and operation

down to 1.8V is required, use pull-up resistor values

below 50k

Ω.

The TPS736xx uses an NMOS pass transistor to

achieve extremely low dropout. When (VIN - VOUT) is

less than the dropout voltage (VDO), the NMOS pass

device is in its linear region of operation and the

input-to-output resistance is the RDS-ON of the NMOS

pass element.

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