SWITCHING SPECIFICATIONS AT T

PARAMETER

SYM DEVICE

MIN TYP MAX UNITS TEST CONDITION

Propagation Delay Time

to Logic Low at Output

t

PHL

55

75

ns

R

( fig 1 )( note2 )

Propagation Delay Time

to Logic High at Output

t

PLH

45

75

ns

R

( fig 1 )( note3 )

Common Mode Transient

Immunity at Logic High

CM

H

ICPL2630

10000

V/

µs

I

Level Output ( fig 2 )( note7 )

ICPL2631

1000 10000

V/

µs

R

Common Mode Transient

Immunity at Logic Low

CM

L

ICPL2630

-10000

V/

µs

V

Level Output ( fig 2 )( note8 )

ICPL2631 -1000 -10000

V/

µs

R

NOTES:-

1

Bypassing of the power supply line is required, with a 0.01

µF ceramic disc capacitor adjacent to

each isolator. The power supply bus for the isolator(s) should be seperate from the bus for any

active loads. Otherwise a larger value of bypass capacitor (up to 0.1

µF) may be needed to supress

regenerative feedback via the power supply.

2

The t

PHL

propagation delay is measured from the 3.75 mA level Low to High transition of the input

current pulse to the 1.5V level on the High to Low transition of the output voltage pulse.

3

The t

current pulse to the 1.5V level on the Low to High transition of the output voltage pulse.

4

Device considered a two terminal device; pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7

and 8 shorted together.

5

Each channel.

6

Measured between pins 1 and 2 shorted together and pins 3 and 4 shorted together.

7

CM

will remain in a high logic state (ie Vout > 2.0V).

8

CM

will remain in a low logic state (ie Vout < 0.8V)

DB92601-AAS/A1

9/10/00

FIG.1 SWITCHING TEST CIRCUIT

2

I

0

I

F

V

O

1.5V

100

Ω

1.5V

5V

t

PHL

t

PLH

V

OL

R

L

V

O

C

8

7

6

5

PULSE

GENERATOR

Z

t

I

F

1

4

3

5V