In Wired-OR applications, the glitch generated as drivers are

released from the bus, is dependent upon the backplane and

parasitic wiring components causing the characteristics of

the glitch to vary in pulse width and amplitude. To accommo-

date this variation the DS3884A features two pins defined as

PS1 and PS2 which allow selection of a 5 ns, 10 ns, 14 ns

and 24 ns filter setting to optimize glitch filtering for a given

situation. The REXT pin is issued in conjunction with the fil-

tering circuitry and requires a 13 k

Ω resistor to ground. For

additional information on Wired-OR glitch, reference Applica-

tion Note AN-774.

The DS3884A driver output configuration is an NPN open

collector which allows Wired-OR connection on the bus.

Each driver output incorporates a Schottky diode in series

with its collector to isolate the transistor output capacitance

from the bus thus reducing the bus loading in the inactive

state. The combined output capacitance of the driver and re-

ceiver input is typically less than 5 pF. The driver also has

high sink current capability to comply with the bus loading re-

quirements defined within IEEE 1194.1 BTL specification.

Backplane Transceiver Logic (BTL) is a signaling standard

that was invented and first introduced by National Semicon-

ductor, then developed by the IEEE to enhance the perfor-

mance of backplane buses. BTL compatible transceivers

feature low output capacitance drivers to minimize bus load-

ing, a 1V nominal signal swing for reduced power consump-

tion and receivers with precision thresholds for maximum

noise immunity. The BTL standard eliminates settling time

delays that severely limit TTL bus performance, and thus

provide significantly higher bus transfer rates. The back-

plane bus is intended to be operated with termination resis-

tors (selected to match the bus impedance) connected to

2.1V at both ends. The low voltage is typically 1V.

Separate ground pins are provided for each BTL output to

minimize induced ground noise during simultaneous switch-

ing.

The device’s unique driver circuitry meets a maximum slew

rate of 0.5V/ns which allows controlled rise and fall times to

reduce noise coupling to adjacent lines.

The transceiver’s high impedance control and driver inputs

are fully TTL compatible.

The receiver is a high speed comparator that utilizes a band-

gap reference for precision threshold control allowing maxi-

mum noise immunity to the BTL 1V signaling level.

Separate QV

the effects of high current switching noise. Output pins

FR1–FR3 are the filtered outputs and R1–R6 are the unfil-

tered outputs. All receiver outputs are fully TTL compatible.

The DS3884A supports live insertion as defined for Future-

bus+ through the LI (Live Insertion) pin. To implement live in-

sertion the LI pin should be connected to the live insertion

power connector. If this function is not supported the LI pin

must be tied to the V

power up/down glitch free protection during power sequenc-

ing.

The DS3884A has two types of power connections in addi-

tion to the LI pin. They are the Logic V

V

provide the supply voltage for the logic and control circuitry.

Multiple connections are provided to reduce the effects of

package inductance and thereby minimize switching noise.

As these pins are common to the V

vice, a voltage difference should never exist between these

pins and the voltage difference between V

tionally, the ESD circuitry between the V

pins except for BTL I/O’s and LI pins requires that any volt-

age on these pins should not exceed the voltage on V

0.5V.

There are three different types of ground pins on the

DS3884A. They are the logic ground (GND), BTL grounds

(B1GND–B6GND) and the Bandgap reference ground

(QGND). All of these ground reference pins are isolated

within the chip to minimize the effects of high current switch-

ing transients. For optimum performance the QGND should

be returned to the connector through a quiet channel that

does not carry transient switching current. The GND and

B1GND–B6GND should be connected to the nearest back-

plane ground pin with the shortest possible path.

Since many different grounding schemes could be imple-

mented and ESD circuitry exist on the DS3884A, it is impor-

tant to note that any voltage difference between ground pins,

cluding power up/down sequencing.

Additional transceivers included in the Futurebus+ / BTL

family are; the DS3883A BTL 9-bit Transceiver, and the

DS3886A BTL 9-bit Latching Data Transceiver featuring

edge triggered latches in the driver which may be bypassed

during a fall-through mode and a transparent latch in the re-

ceiver.

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