Pin Description

Pin Name

Number

Input/

Description

of Pins

Output

A0–A8

9

I/O

TTL TRI-STATE receiver output and driver input

B0–B8

9

I/O

BTL receiver input and driver output

B0GND–B8GND

9

NA

Parallel driver grounds reduce ground bounce due to high current

switching of driver outputs. (Note 11)

CD

1

I

Chip Disable

GND

2

NA

Ground for switching circuits. (Note 11)

LI

1

NA

Power supply for live insertion. Boards that require live insertion should

connect LI to the live insertion pin on the connector. (Note 12)

NC

8

NA

No Connect

QGND

1

NA

Ground for receiver input bandgap reference and non-switching circuits.

(Note 11)

QV

CC

1NA

V

T/R

1

I

Transmit/Receive — transmit (An to Bn), receive (Bn to An)

V

CC

2NA

V

Note 11: The multiplicity of parallel ground paths reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients

on the ground path. The various ground pins can be tied together provided that the external ground has low inductance. (i.e., ground plane with power pins and many

signal pins connected to the backplane ground.) If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND

from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A volt-

age offset between their grounds will degrade the noise margin.

CD

T/R

An

Bn (BTL)

HX

Z

H

LLL

H

LL

H

L

LH

H

L

LHL

H

X = High or low logic state

Z = High impedance state

L = Low state

H = High state

Package Thermal Characteristics

Linear Feet per

Minute Air Flow

(LFPM)

θ

44-Pin

PQFP

082

225

68

500

60

900

53

Note 13: The above values are typical values and are different from the Ab-

solute Maximum Rating values, which include guardbands.

www.national.com

5