MSP430F412 datasheet(15/55 Pages) TI

15 / 55 page

MSP430x41x

MIXED SIGNAL MICROCONTROLLER

SLAS340G − MAY 2001 − REVISED JUNE 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature

number SLAU056.

oscillator and system clock

The clock system in the MSP430x41x family of devices is supported by the FLL+ module that includes support

for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency

crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and

low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction

with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.

The internal DCO provides a fast turn-on clock source and stabilizes in less than 6

µs. The FLL+ module

provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.

D Main clock (MCLK), the system clock used by the CPU.

D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed

level or user selectable level (MSP430x415 & MSP430x417 only) and supports both supply voltage supervision

(the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not

have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC

reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

digital I/O

There are six 8-bit I/O ports implemented—ports P1 through P6:

D All individual I/O bits are independently programmable.

D Any combination of input, output, and interrupt conditions is possible.

D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

D Read/write access to port-control registers is supported by all instructions.

Basic Timer1

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both

timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and

clock for the LCD module.

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD

controller has dedicated data memory to hold segment drive information. Common and segment signals are

generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

MSP430F412 Datasheet(PDF) 15 Page - Texas Instruments

MSP430F412 Datasheet(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL