TMS320DM8148 datasheet(33/376 Pages) TI1

33 / 376 page

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

Table 2-7. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters

C674x DSP

START

SIZE

DEVICE NAME

END ADDRESS

START

END ADDRESS

ADDRESS

(HEX)

ADDRESS (HEX)

(HEX)

0x481C_E000

0x481C_FFFF

8KB

DCAN0 Support Registers

0x481D_0000

0x481D_1FFF

8KB

DCAN1 Peripheral Registers

0x481D_2000

0x481D_3FFF

8KB

DCAN1 Support Registers

0x481D_4000

0x481D_5FFF

0x081D_4000

0x081D_5FFF

8KB

Reserved

0x481D_6000

0x481D_6FFF

0x081D_6000

0x081D_6FFF

4KB

Reserved

0x481D_7000

0x481D_7FFF

0x081D_7000

0x081D_7FFF

4KB

Reserved

0x481D_8000

0x481E_7FFF

64KB

MMC/SD/SDIO1 Peripheral Registers

0x481E_8000

0x481E_8FFF

4KB

MMC/SD/SDIO1 Support Registers

0x481E_9000

0x481F_FFFF

0x081E_9000

0x081F_FFFF

52KB

Reserved

0x4820_0000

0x4820_0FFF

4KB

Interrupt controller(1)

0x4820_1000

0x4823_FFFF

0x0820_1000

0x0823_FFFF

252KB

Reserved(1)

0x4824_0000

0x4824_0FFF

4KB

MPUSS config register(1)

0x4824_1000

0x4827_FFFF

0x0824_1000

0x0827_FFFF

252KB

Reserved(1)

0x4828_0000

0x4828_0FFF

4KB

Reserved(1)

0x4828_1000

0x482F_FFFF

0x0828_1000

0x082F_FFFF

508KB

Reserved(1)

0x4830_0000

0x48FF_FFFF

0x0830_0000

0x08FF_FFFF

13MB

Reserved

(1)

These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only

for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.

2.12.5 DDR DMM TILER Extended Addressing Map

The TILER includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access

the frame buffer in rotated and mirrored views. shows the details of the TILER Extended Address

Mapping. This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems.

However, other masters can access any one single view through the 512-MB TILER region in the base

4GByte address memory map.

Table 2-8. DDR DMM TILER Extended Address Mapping

START ADDRESS

END ADDRESS

BLOCK NAME

SIZE

DESCRIPTION

(HEX)

TILER View 0

0x1 0000_0000

0x1 1FFF_FFFF

512MB

Natural 0° View

TILER View 1

0x1 2000_0000

0x1 3FFF_FFFF

512MB

0° with Vertical Mirror

View

TILER View 2

0x1 4000_0000

0x1 5FFF_FFFF

512MB

0° with Horizontal Mirror

View

TILER View 3

0x1 6000_0000

0x1 7FFF_FFFF

512MB

180° View

TILER View 4

0x1 8000_0000

0x1 9FFF_FFFF

512MB

90° with Vertical Mirror

View

TILER View 5

0x1 A000_0000

0x1 BFFF_FFFF

512MB

270° View

TILER View 6

0x1 C000_0000

0x1 DFFF_FFFF

512MB

90° View

TILER View 7

0x1 E000_0000

0x1 FFFF_FFFF

512MB

90° with Horizontal Mirror

View

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