 2016 Microchip Technology Inc.

DS20005372A-page 9

HV2662 / HV2762

3.0

FUNCTIONAL DESCRIPTION

FIGURE 3-1:

LOGIC TIMING WAVEFORMS

DATA IN

DIN

LE

CLOCK

DATA OUT

DOUT

OFF

ON

CLR

V

OUT

(typ)

50%

50%

50%

50%

t

WLE

t

SD

50%

50%

t

SU

t

h

t

OFF

50%

t

DO

t

ON

t

WCL

D

N - 1

D

N

D

N + 1

50%

50%

90%

10%

TABLE 3-1:

TRUTH TABLE

D01

D1

...

D15

D16

...

D232

LE3

CLR4 SW05,6

SW1

...

SW15

SW16

...

SW23

L

-

...

-

-

...

-

L

L

OFF

-

...

-

-

...

-

H

-

-

-

-

L

L

ON

-

-

-

-

-

L

-

-

-

L

L

-

OFF

-

-

-

-

H

-

-

-

L

L

-

ON

-

-

-

-

-

-

-

-

L

L

-

-

-

-

-

-

-

-

-

-

L

L

-

-

-

-

-

-

-

L

-

-

L

L

-

-

OFF

-

-

-

-

H

-

-

L

L

-

-

ON

-

-

-

-

-

L

-

L

L

-

-

-

OFF

-

-

-

-

H

-

L

L

-

-

-

ON

-

-

-

-

-

-

L

L

-

-

-

-

-

-

-

-

-

-

L

L

-

-

-

-

-

-

-

-

-

-

L

L

-

-

-

-

-

-

-

-

-

-

L

L

-

-

-

-

-

-

-

-

-

L

L

L

-

-

-

-

OFF

-

-

-

-

H

L

L

-

-

-

-

ON

X

X

X

X

X

X

X

H

L

HOLD PREVIOUS STATE

X

X

X

X

X

X

X

X

H

ALL SWITCHES OFF

Note 1: Serial data is clocked in on the L to H transition of the CLK

2: DOUT is high when data in the register 23 is high.

3: Shift registers clocking has no effect on the switch states if LE is high.

4: The CLR clear input overrides all other inputs.

5: The 24 switches operate independently.

6: All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the

shift registers data flow through the latch.