EMC1704 datasheet(39/68 Pages) MICROCHIP

39 / 68 page

High-Side Current-Sense and Multiple 1°C Temperature Monitor

DS20005239A

EMC1704

DATASHEET

5.4

Status Register

The Status Register reports general error conditions. To identify specific channels, refer to

Section 5.10, Section 5.15, Section 5.16, and Section 5.17. The individual Status Register bits are

cleared when the appropriate High Limit, Low Limit, or Crit Limit status register has been read or

cleared.

Bit 7 - BUSY - This bit indicates that one of the ADCs is currently converting. This bit does not cause

either the ALERT or THERM pins to be asserted.

Bit 6 - PEAK - This bit is set when the Peak Detector circuitry has detected a current peak that is

greater than the programmed threshold for longer than the programmed duration. This bit is not sticky

and will be cleared when the condition has been removed. When set, the THERM pin or ALERT pin

(Comparator mode only) may be asserted (see Section 5.19).

Bit 5 - GPIO - This bit is set when the GPIO pin changes state when configured as a GPIO input.

When set, the ALERT pin is asserted. This bit will be sticky and is cleared when read.

Bit 4 - HIGH - This bit is set when any of the temperature channels meets or exceeds its programmed

high limit. This bit will also be set if the VSENSE or VSOURCE channels meet or exceed their respective

high limits. See the High Limit Status Register for specific channel information (Section 5.15). When

set, the ALERT pin is asserted.

Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low

limit. This bit will also be set if the VSENSE or VSOURCE channels drop below their respective low limits.

See the Low Limit Status Register for specific channel information (Section 5.16). When set, the

ALERT pin is asserted.

Bit 2 - FAULT - This bit is set when a diode fault is detected on any of the external diode channels.

See the External Diode Fault Register for specific channel information (Section 5.10). When set, the

ALERT pin is asserted.

Bit 1 - CRIT - This bit is set when any of the temperature channels meets or exceeds its programmed

Tcrit limit. This bit will also be set if the VSENSE or VSOURCE channels meet or exceed their respective

Vcrit limits (see the Section 5.17, "Crit Limit Status Register" for specific channel information). When

set, the THERM pin is asserted. This bit is not sticky and will be cleared when the error condition has

been removed.

0100_0000_000b

40_00h

0100_0001_000b

41_00h

127

0111_1111_000b

7F_00h

127.875

0111_1111_111b

7F_E0h

Table 5.4 Status Register

ADDR

R/W

DEFAULT

02h

Status

BUSY

PEAK

GPIO

HIGH

LOW

FAULT

CRIT

00h

34h

Table 5.3 Temperature Data Format (continued)

TEMPERATURE (°C)

BINARY

HEX (AS READ BY REGISTERS)

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