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LM5104M Datasheet(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # LM5104M
Description  High Voltage Half-Bridge Gate Driver with Adaptive Delay
PDF  12 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM5104M Datasheet(HTML) 8 Page - National Semiconductor (TI)

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LM5104 Waveforms
Operational Description
ADAPTIVE SHOOT-THROUGH PROTECTION
LM5104 is a high voltage, high speed dual output driver
designed to drive top and bottom MOSFET’s connected in
synchronous buck or half-bridge configuration, from one ex-
ternally provided PWM signal. LM5104 features adaptive
delay to prevent shoot-through current through top and bot-
tom MOSFETs during switching transitions. Referring to the
timing diagram Figure 3, the rising edge of the PWM input
(IN) turns off the bottom MOSFET (LO) after a short propa-
gation delay (t
P). An adaptive circuit in the LM5104 monitors
the bottom gate voltage (LO) and triggers a programmable
delay generator when the LO pin falls below an internally set
threshold (
≈ Vdd/2). The gate drive of the upper MOSFET
(HO) is disabled until the deadtime expires. The upper gate
is enabled after the TIMER delay (t
P+TRT) , and the upper
MOSFET turns-on. The additional delay of the timer pre-
vents lower and upper MOSFETs from conducting simulta-
neously, thereby preventing shoot-through.
A falling transition on the PWM signal (IN) initiates the turn-
off of the upper MOSFET and turn-on of the lower MOSFET.
A short propagation delay (t
P) is encountered before the
upper gate voltage begins to fall. Again, the adaptive shoot-
through circuitry and the programmable deadtime TIMER
delays the lower gate turn-on time. The upper MOSFET gate
voltage is monitored and the deadtime delay generator is
triggered when the upper MOSFET gate voltage with respect
to ground drops below an internally set threshold (
≈ Vdd/2).
The lower gate drive is momentarily disabled by the timer
and turns on the lower MOSFET after the deadtime delay
expires (t
P+TRT).
20089005
FIGURE 3. Application Timing Waveforms
www.national.com
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