PCM1608YSLASH2K datasheet(14/29 Pages) TI

14 / 29 page

PCM1608

SBAS164A

The Read cycle starts by setting the R/W bit of the control

word to “1”, and setting all of the IDX[6:0] bits to “0”.

All subsequent bits input on the MDI are ignored while ML

is set to “0”. For the first eight clocks of the Read cycle,

MDO is set to a high-impedance state. This is followed by

a sequence of 8-bit words, each corresponding the data

contained in Control Registers 1 through N, where N is

defined by the REG[6:0] bits in Control Register 11. The

Read cycle is completed when ML is set to “1”, immediately

after the MC clock cycle for the least significant bit of

Control Register N has completed.

CONTROL INTERFACE TIMING REQUIREMENTS

Figure 9 shows a detailed timing diagram for the Serial

Control interface. Pay special attention to the setup and hold

times, as well as tMLS and tMLH, which define minimum delays

between edges of the ML and MC clocks. These timing

parameters are critical for proper control port operation.

SYMBOL

PARAMETER

MIN

MAX

UNITS

tMCY

MC Pulse Cycle Time

100

tMCL

MC Low Level Time

tMCH

MC High Level Time

tMHH

ML High Level Time

300

tMLS

ML Falling Edge to MC Rising Edge

tMLH

ML Hold Time(1)

tMDH

MDI Hold Time

tMDS

MDL Set Up Time

tMOS

MC Falling Edge to MDSO Stable

NOTE: (1) MC rising edge for LSB to ML rising edge.

FIGURE 9. Control Interface Timing.

50% of V

MDI

MDO

MLS

MCH

MCY

MOS

MDS

MCH

MCL

MHH

MLH

LSB

PCM1608Y/2K Datasheet(PDF) 14 Page - Texas Instruments

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