PCM3010

SLES055 – NOVEMBER 2002

28

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typical circuit connection

The following figure illustrates typical circuit connection.

VCC1

20

19

18

17

16

15

14

13

5

6

7

8

9

10

11

12

AGND1

FMT0

FMT1

TEST

LRCK

BCK

DIN

AGND2

DOUT

DEMP0

DEMP1

PDWN

SCKI

DGND

VDD

L-Ch IN

Format 0

Clock

De-emphasis 0

(See Note C)

Control

VINL

24

23

22

21

1

2

3

4

VINR

VREF1

VREF2

VCOM

VOUTL

VOUTR

VCC2

+

+

(See Note B)

+

(See Note B)

+

(See Note A)

+

NOTES: A. 0.1

µF ceramic and 10 µF electrolytic capacitors typical, depending on power supply quality and pattern layout.

B. 0.1

µF ceramic and 10 µF electrolytic capacitors are recommended.

C. 1

µF electrolytic capacitor typical, gives 8-Hz cutoff frequency of input HPF in normal operation and gives settling time with

20 ms (1

µF × 20 kΩ) time constant in power ON and power down OFF period.

D. 10

µF electrolytic capacitor typical, gives 2-Hz cutoff frequency for 10-kΩ post-LPF input resistance in normal operation and

gives settling time with 100 ms (10

µF × 10 kΩ) time constant in power ON and power down OFF period.

R-Ch IN

0 V

3.3 V

5 V

Format 1

L/R Clock

Data IN

Bit Clock

Control

Data

+

(See Note B)

(See Note D)

(See Note D)

(See Note A)

+

+

+

(See Note C)

Post LPF

Post LPF

De-emphasis 1

Power Down

System Clock

Clock

Data OUT

Data

+

(See Note A)

design and layout considerations in application

The digital and analog power supply lines to the PCM3010 should be bypassed to the corresponding ground

pins, with 0.1-

µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the

dynamic performance of the ADC and the DAC.

Although the PCM3010 has three power lines to maximize the potential of dynamic performance, using one

supply trouble, like latch-up or power supply sequencing problems.

grounding (AGND1, AGND2, DGND)

To maximize the dynamic performance of the PCM3010, the analog and digital grounds are not connected

internally. These points should have very low impedance to avoid digital noise feeding back into the analog

ground. They should be connected directly to each other under the connected parts to reduce the potential for

noise problems.