TPS22993 datasheet(21/38 Pages) TI1

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Auto-Inc.

SDA

SCL

ST A6 A5 A4 A3 A2 A1 A0 0

A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SP

Start

Slave Address

W/R

Ack. from slave

Sub Address

Ack

from

slave

Ack

from

slave

Ack

from

slave

Stop

Data to Register N

Data Byte

TPS22993

www.ti.com

SLVSCA3A – NOVEMBER 2013 – REVISED MARCH 2014

10.1.9 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a

discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic

capacitor, CIN, placed close to the terminals, is usually sufficient. Higher values of CIN can be used to further

reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have

an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the

fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive

voltage drop.

10.1.10 Output Capacitor (Optional)

Due to the integrated body diode of the NMOS switch, a CIN greater than CL is highly recommended. A CL

greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current

flow through the body diode from VOUT to VIN. A CIN to CL ratio of at least 10 to 1 is recommended for minimizing

VIN dip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio

of at least 100 to 1 is recommended to minimize VIN dip caused by inrush currents during startup.

10.1.11 I2C Protocol

The following section will cover the standard I2C protocol used in the TPS22993. In the I2C protocol, the following

basic blocks are present in every command (except for the SwitchALLTM command):

•

Start/stop bit – marks the beginning and end of each command.

•

Slave address – the unique address of the slave device.

•

Sub address – this includes the register address and the auto-increment bit.

•

Data byte – data being written to the register. Eight bits must always be transferred even if a single bit is

being written or read.

•

Auto-increment bit – setting this bit to ‘1’ turns on the auto-increment functionality; setting this bit to ‘0’ turns

off the auto-increment functionality.

•

Write/read bit – this bit signifies if the command being sent will result in reading from a register or writing to a

•

Acknowledge bit – this bit signifies if the master or slave has received the preceding data byte.

10.1.11.1

Start and Stop Bit

In the I2C protocol, all commands contain a START bit and a STOP bit. A START bit, defined by high to low

transition on the SDA line while SCL is high, marks the beginning of a command. A STOP bit, defined by low to

high transition on the SDA line while SCL is high, marks the end of a command. The START and STOP bits are

generated by the master device on the I2C bus. The START bit indicates to other devices that the bus is busy,

and some time after the STOP bit the bus is assumed to be free.

10.1.11.2

Auto-increment Bit

The auto-increment feature in the I2C protocol allows users to read from and write to consecutive registers in

fewer clock cycles. Since the register addresses are consecutive, this eliminates the need to resend the register

address. The I2C core of the device automatically increments the register address pointer by one when the auto-

increment bit is set to ‘1’. When this bit is set to ‘0’, the auto-increment functionality is disabled.

10.1.11.3

Write Command

During the write command, the write/read bit is set to ‘0’, signifying that the register in question will be written to.

Figure 33 the composition of the write protocol to a single register:

Figure 33. Data Write to a Single Register

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