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MB87P2020 Datasheet(PDF) 21 Page - fujitsu semiconductor |
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MB87P2020 Datasheet(HTML) 21 Page - fujitsu semiconductor |
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21 / 356 page  Graphic Controller Overview Clock supply and generation Page 21 3 Clock supply and generation GDC has a flexible clocking concept where four input clocks (OSC_IN/OUT, DIS_PIXCLK, ULB_CLK, RCLK) can be used as clock source for Core clock (CLKK) and Display clock (CLKD). The user can choose by software whether to take the direct clock input or the output of an APLL independ- ent for Core- and Display clock. Both output clocks have different dividers programmable by software (DIV x for CLKD and DIV z for CLKK). The clock gearing facilities offer the possibility to scale system performance and power consumption as needed. Beside these two configurable clocks (CLKK and CLKD) GDC needs two additional internal clocks: CLKM and CLKV (see also figure 3-1). CLKV is exclusively for video interface and is connected to input clock pin VSC_CLKV. CLKM is used for User Logic Bus (ULB) interface and is connected to input clock ULB_CLK. As already mentioned ULB_CLK can also be used to build CLKK and/or CLKD. Table 3-1 shows all clocks used by GDC with their requirements. Table 3-1: Clock supply Clock Type Symbol Requirements Unit Min Typ Max XTAL clock input OSC_IN, OSC_OUT 12a -64 MHz Reserve clock input RCLK ULB_CLKb -64 MHz ULB clock input ULB_CLK - - 64 MHz Pixel clock input DIS_PIXCLK - - 54 MHz Video clock input VSC_CLKV - - 54c MHz Core clock internal CLKK ULB_CLK - 64 MHz Display clock internal CLKD - - 54 MHz Video clock internal CLKV - - 54c MHz ULB clock internal CLKM - - 64 MHz (Jasmine only) MUL y DIV x DIV z OSC_IN/OUT DIS_PIXCLK ULB_CLK RCLK PLL Clock Direct Clock VSC_CLKV System Clock Prescaler Pixel Clock Prescaler invert option invert option CLKK CLKM CLKV CLKD APLL Figure 3-1: Clock gearing and distribution |
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