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OPA642PB Datasheet(PDF) 13 Page - Texas Instruments |
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OPA642PB Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 16 page ![]() ® OPA642 13 FIGURE 8. DC Coupled, Inverting Gain of –2, with Output Offset Adjustment. closest integer for minimum noise figure. This optimum turns ratio is calculated by This optimum will depend strongly on the amplifier and configuration selected. the offset control is best applied as an inverting summing signal. If the signal path is intended to be inverting, applying the offset control to the non-inverting input can be consid- ered. For a DC coupled signal, the DC offset signal can, in some configurations, set up a DC current back into the source that must be considered. An adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 8 shows one example of an offset adjustment for a DC coupled signal path that will have minimum impact on the signal frequency response. In this case, the input is brought in to an inverting gain resistor with the DC adjustment an additional current summed into the inverting node. The resistor network setting this current is much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence the frequency response. FIGURE 7. Reduced Noise Figure Circuit. DC OFFSET CONTROL The OPA642 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. The high grade (B) version of any package type provides less than 1mV input offset voltage. To take full advantage of this low input offset voltage, a careful attention to input bias current cancellation is also required. The high speed input stage for the OPA642 has a relatively high input bias current (25 µA typ into the pins) but with a very close match between the two input currents—typically 100nA input offset current. The total output offset voltage may be considerably reduced by match- ing the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 175 Ω series resistor into the non-inverting input from the 50 Ω terminating resis- tor. When the 50 Ω source resistor is DC coupled, this will increase the source impedance for the non-inverting input bias current to 200 Ω. Since this is now equal to the imped- ance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402 Ω feedback resistor, this output error will now be less than 3 µA • 402 Ω = 1.2mV. A fine scale output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, R F 1k Ω ±200mV Output Adjustment = – = –2 Supply Decoupling Not Shown 5k Ω 5k Ω 328 Ω 0.1µF R G 500 Ω V I 20k Ω 10k Ω 0.1µF –5V +5V OPA642 +5V –5V V O V O V I R F R G THERMAL ANALYSIS The OPA642 will not require heatsinking under most oper- ating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175 °C. Operating junction temperature (T J) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissi- pated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition P DL = VS 2/(4 • R L) where RL includes feedback network loading. Eq. 4 N OPT = Nearest Integer E N /I BN • RS /2 () () 402 Ω 50 Ω A V = 7V/V [16.9dB] Supply Decoupling Not Shown 6.3dB Noise Figure R S = 50Ω 1:7 OPA642 402 Ω 2.4k Ω 50 Ω Load |
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