DS90C363 Pin Description — FPD Link Transmitter

Pin Name

I/O

No.

Description

TxIN

I

21

TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

TxOUT+

O

3

Positive LVDS differentiaI data output.

TxOUT−

O

3

Negative LVDS differential data output.

FPSHIFT IN

I

1

TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.

R_FB

I

1

Programmable strobe select.

RTxCLK OUT+

O

1

Positive LVDS differential clock output.

TxCLK OUT−

O

1

Negative LVDS differential clock output.

PWR DWN

I

1

TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at

power down.

V

CC

I

3

Power supply pins for TTL inputs.

GND

I

4

Ground pins for TTL inputs.

PLL V

CC

I

1

Power supply pin for PLL.

PLL GND

I

2

Ground pins for PLL.

LVDS V

CC

I

1

Power supply pin for LVDS outputs.

LVDS GND

I

3

Ground pins for LVDS outputs.

DS012886-11

C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max

Tppos — Transmitter output pulse position (min and max)

RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)

Cable Skew — typically 10 ps–40 ps per foot, media dependent

Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.

Note 11: ISI is dependent on interconnect length; may be zero.

FIGURE 19. Receiver LVDS Input Skew Margin

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