 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS90C383 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DS90C383 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
|
|
1 / 20 page  DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link—65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signal- ing) data streams. A phase-locked transmit clock is transmit- ted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver con- verts the LVDS data streams back into 28 bits of LVCMOS/ LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is of- fered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmit- ter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge trans- mitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n 20 to 65 MHz shift clock support n Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe) n Single 3.3V supply n Chipset (Tx + Rx) power consumption < 250 mW (typ) n Power-down mode (< 0.5 mW total) n Single pixel per clock XGA (1024x768) ready n Supports VGA, SVGA, XGA and higher addressability. n Up to 227 Megabytes/sec bandwidth n Up to 1.8 Gbps throughput n Narrow bus reduces cable size and cost n 290 mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 56-lead TSSOP package. n Also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package n Falling edge data strobe Receiver n Compatible with TIA/EIA-644 LVDS standard n ESD rating >7kV n Operating Temperature: −40˚C to +85˚C Block Diagrams TRI-STATE® is a registered trademark of National Semiconductor Corporation. Typical Application DS012887-2 November 2000 © 2000 National Semiconductor Corporation DS012887 www.national.com |
Similar Part No. - DS90C383 |
|
Similar Description - DS90C383 |
|
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
