2

Functional Diagram

TRUTH TABLE

OPERATING

MODE

INPUTS

OUTPUT

CP

MR

S1

S0

DSR

DSL

Reset (Clear)

X

L

X

X

X

X

X

LLLL

Hold (Do Nothing)

X

H

l (Note 1)

l (Note 1)

X

X

X

Shift Left

↑

H

h

l (Note 1)

X

l

X

L

↑

H

h

l (Note 1)

X

h

X

H

Shift Right

↑

H

l (Note 1)

h

l

X

X

L

↑

H

l (Note 1)

h

h

X

X

H

Parallel Load

↑

Hh

h

X

X

H = High Voltage Level,

h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,

L = Low Voltage Level,

l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,

Transition,

X = Don’t Care,

↑ = Transition from Low to High Level

NOTE:

1. The High-to-Low transition of the S0 and S1 Inputs on the ’HC194 and CD74HCT194 should take place only while CP is High for

Conventional Operation.

14

12

13

15

7

6

3

4

5

GND = 8

2

9

10

1

11

DSL

DSR

S0

S1

MR

CP

CD54HC194, CD74HC194, CD74HCT194