Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

TCIT

TxCLK IN Transition Time

(Figure 5 )

5ns

TCIP

TxCLK IN Period

(Figure 6 )

14.7

T

55.6

ns

TCIH

TxCLK IN High Time

(Figure 6 )

0.35T

0.5T

0.65T

ns

TCIL

TxCLK IN Low Time

(Figure 6 )

0.35T

0.5T

0.65T

ns

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

LLHT

LVDS Low-to-High Transition Time

(Figure 4 )

0.75

1.5

ns

LHLT

LVDS High-to-Low Transition Time

(Figure 4 )

0.75

1.5

ns

TPPos0

Transmitter Output Pulse Position for Bit 0

(Figure 11 ) (Note 5)

f = 65 MHz

−0.30

0

0.20

ns

TPPos1

Transmitter Output Pulse Position for Bit 1

1.90

2.20

2.40

ns

TPPos2

Transmitter Output Pulse Position for Bit 2

4.10

4.40

4.60

ns

TPPos3

Transmitter Output Pulse Position for Bit 3

6.30

6.60

6.80

ns

TPPos4

Transmitter Output Pulse Position for Bit 4

8.50

8.80

9.00

ns

TPPos5

Transmitter Output Pulse Position for Bit 5

10.70

11.00

11.20

ns

TPPos6

Transmitter Output Pulse Position for Bit 6

12.90

13.20

13.40

ns

TPPos0

Transmitter Output Pulse Position for Bit 0

(Figure 11 ) (Note 5)

f = 40 MHz

−0.35

0

0.35

ns

TPPos1

Transmitter Output Pulse Position for Bit 1

3.22

3.57

3.92

ns

TPPos2

Transmitter Output Pulse Position for Bit 2

6.79

7.14

7.49

ns

TPPos3

Transmitter Output Pulse Position for Bit 3

10.36

10.71

11.06

ns

TPPos4

Transmitter Output Pulse Position for Bit 4

13.93

14.28

14.63

ns

TPPos5

Transmitter Output Pulse Position for Bit 5

17.51

17.86

18.21

ns

TPPos6

Transmitter Output Pulse Position for Bit 6

21.08

21.43

21.78

ns

TPPos0

Transmitter Output Pulse Position for Bit 0

(Figure 11 ) (Note 5)

f = 32.5

MHz

−0.40

0

0.40

ns

TPPos1

Transmitter Output Pulse Position for Bit 1

4.00

4.40

4.80

ns

TPPos2

Transmitter Output Pulse Position for Bit 2

8.40

8.80

9.20

ns

TPPos3

Transmitter Output Pulse Position for Bit 3

12.80

13.20

13.60

ns

TPPos4

Transmitter Output Pulse Position for Bit 4

17.20

17.60

18.00

ns

TPPos5

Transmitter Output Pulse Position for Bit 5

21.60

22.00

22.40

ns

TPPos6

Transmitter Output Pulse Position for Bit 6

26.00

26.40

26.80

ns

TSTC

TxIN Setup to TxCLK IN

(Figure 6 )

2.5

ns

THTC

TxIN Hold to TxCLK IN

(Figure 6 )

0ns

TCCD

TxCLK IN to TxCLK OUT Delay

(Figure 7 ) T

3

5.5

ns

TxCLK IN to TxCLK OUT Delay

(Figure 7 )

3

7.0

ns

TJCC

Transmitter Jitter Cycle-to-Cycle

(Figures 12, 13 ) (Note 6)

f = 65 MHz

175

225

ps

f = 40 MHz

240

380

ps

f = 32.5

MHz

260

400

ps

TPLLS

Transmitter Phase Lock Loop Set

(Figure 8 )

10

ms

TPDD

Transmitter Power Down Delay

(Figure 10 )

100

ns

Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This param-

eter is functionality tested only on Automatic Test Equipment (ATE).

Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a cycle-

to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips

currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.

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