DS90CF386 MTD56 Package Pin Description—24-Bit FPD Link Receiver

Pin Name

I/O

No.

Description

RxIN+

I

4

Positive LVDS differentiaI data inputs.

RxIN−

I

4

Negative LVDS differential data inputs.

RxOUT

O

28

TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control

lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data

Enable).

RxCLK IN+

I

1

Positive LVDS differential clock input.

RxCLK IN−

I

1

Negative LVDS differential clock input.

RxCLK OUT

O

1

TTL Ievel clock output. The falling edge acts as data strobe.

PWR DOWN

I

1

TTL level input. When asserted (low input) the receiver outputs are low.

V

CC

I

4

Power supply pins for TTL outputs.

GND

I

5

Ground pins for TTL outputs.

PLL V

CC

I

1

Power supply for PLL.

PLL GND

I

2

Ground pin for PLL.

LVDS V

CC

I

1

Power supply pin for LVDS inputs.

LVDS GND

I

3

Ground pins for LVDS inputs.

DS90CF366 MTD48 Package Pin Description—18-Bit FPD Link Receiver

Pin Name

I/O

No.

Description

RxIN+

I

3

Positive LVDS differentiaI data inputs.

RxIN−

I

3

Negative LVDS differential data inputs.

RxOUT

O

21

TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,

FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).

RxCLK IN+

I

1

Positive LVDS differential clock input.

RxCLK IN−

I

1

Negative LVDS differential clock input.

RxCLK OUT

O

1

TTL Ievel clock output. The falling edge acts as data strobe.

PWR DOWN

I

1

TTL level input. When asserted (low input) the receiver outputs are low.

V

CC

I

4

Power supply pins for TTL outputs.

GND

I

5

Ground pins for TTL outputs.

PLL V

CC

I

1

Power supply for PLL.

PLL GND

I

2

Ground pin for PLL.

LVDS V

CC

I

1

Power supply pin for LVDS inputs.

LVDS GND

I

3

Ground pins for LVDS inputs.

DS90CF386 — 64 ball FBGA package Pin Description —

FPD Link Receiver

Pin Name

I/O

No.

Description

RxIN+

I

4

Positive LVDS differentiaI data inputs.

RxIN−

I

4

Negative LVDS differential data inputs.

RxOUT

O

28

TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,

FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).

RxCLK IN+

I

1

Positive LVDS differential clock input.

RxCLK IN−

I

1

Negative LVDS differential clock input.

FPSHIFT OUT

O

1

TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.

PWR DOWN

I

1

TTL level input. When asserted (low input) the receiver outputs are low.

V

CC

I

4

Power supply pins for TTL outputs.

GND

I

5

Ground pins for TTL outputs.

PLL V

CC

I

1

Power supply for PLL.

PLL GND

I

2

Ground pin for PLL.

LVDS V

CC

I

1

Power supply pin for LVDS inputs.

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