PCM1802

SLES023B – DECEMBER 2001 – REVISED MARCH 2002

16

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PRINCIPLES OF OPERATION

interface timing

Figure 25 and Figure 27 illustrate the interface timing in slave mode and master mode, respectively.

FORMAT 0: FMT[1:0] = 00

24-Bit, MSB-First, Left-Justified

BCK

LRCK

Right-Channel

Left-Channel

DOUT

1

22 23 24

3

2

1

MSB

LSB

22 23 24

3

2

1

MSB

LSB

FSYNC

FORMAT 1: FMT[1:0] = 01

24-Bit, MSB-First, IIS

LRCK

Right-Channel

Left-Channel

BCK

DOUT

22 23 24

3

2

1

MSB

LSB

22 23 24

3

2

1

MSB

LSB

FSYNC

FORMAT 2: FMT[1:0] = 10

24-Bit, MSB-First, Right-Justified

LRCK

Right-Channel

Left-Channel

BCK

DOUT

24

22 23 24

3

2

1

MSB

LSB

22 23 24

3

2

1

MSB

LSB

FSYNC

FORMAT 3: FMT[1:0] = 11

20-Bit, MSB-First, Right-Justified

LRCK

Right-Channel

Left-Channel

BCK

DOUT

20

18 19 20

3

2

1

MSB

LSB

18 19 20

3

2

1

MSB

LSB

FSYNC

Figure 24. Audio Data Format (Slave Mode: FSYNC, LRCK, BCK Work as Inputs)