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SY89834U Datasheet(PDF) 4 Page - Micrel Semiconductor

Part # SY89834U
Description  2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR
PDF  10 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY89834U Datasheet(HTML) 4 Page - Micrel Semiconductor

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PRELIMINARY
Precision Edge™
SY89834U
Micrel
V
CC = 2.5V ±5% or 3.3V ±10%, TA = –40°C to +85°C
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Frequency
Input tr /tf ≥ 350ps, Note 2
1.0
GHz
t
PLH
Propagation Delay (IN1, IN2-to-Q)
Note 4
200
320
500
ps
t
PHL
t
SW
Switchover Time (SEL-to-Q)
200
320
500
ps
t
SKEW
Within-Device Skew
Note 5
520
ps
Part-to-Part Skew
300
ps
t
JITTER
Cycle-to-Cycle Jitter
Note 6
1
ps(rms)
Total Jitter
Note 7
1
ps(pk-pk)
DC
Duty Cycle
Input t
r/tf ≥ 350ps, Note 8
45
50
55
%
t
S
Set-Up Time (EN to IN1, IN2)
Note 9 and Note 10
300
ps
t
H
Hold Time (EN to IN1, IN2)
Note 9 and Note 10
500
ps
t
r, tf
Output Rise/Fall Times
70
140
225
ps
(20% to 80%)
Note 1.
Measured with a 2.0V input signal, 50% duty cycle, all PECL loading with 50
Ω to V
CC–2V. Output swing is ≥ 400mV.
Note 2.
Specification for packaged product only.
Note 3.
fMAX is defined as the maximum input frequency while enduring a valid output. fMAX is limited by the input stage.
Note 4.
V
IH = 2.0V, VIL = 0.8V, 50% duty cycle. Delay measured at 100MHz from the crossing of the input signal with VCC/2 as the crossing of the
differential output signal. See Figure 1.
Note 5.
Skew is measured between outputs under identical transitions.
Note 6.
Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs.
T
JITTER_CC = Tn – Tn+1, where T is the time between rising edges of the output signal.
Note 7.
Total jitter definition: with an ideal clock input frequency of
≤ f
MAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
Note 8.
If tr/tf is less than 350ps, the duty cycle distortion will increase beyond the duty cycle limits.
Note 9.
Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applica-
tions set-up and hold times do not apply.
Note 10. See
“Timing Diagrams,” Figure 1a.
AC ELECTRICAL CHARACTERISTICS(Notes 1, 2)



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