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11.2.Receive Buffer Ring

Incoming packets are placed by the NIC into the Receive Buffer Ring to await processing. As each packet

is processed, it is then removed from the ring. The NIC allocates an area of memory to use as the buffer

ring during initialization. Because ring pointers are located on the chip, the buffer management scheme

works at a high efficiency. The DMA channels can transfer data at 10 Mbyte per second. The second

DMA or the remote DMA channel removes packets from the rings after the packets have been processed.

Though the receive buffer ring allows packets to be processed in the order of arrival, it is not a FIFO buffer.

It is just a portion of memory that works effectively as a FIFO buffer

The four on-chip pointers that control the ring are the page start (PSTART) pointer, page stop (PSTOP)

pointer, current page (CURR) pointer and boundary (BNRY) pointer.

The PSTART and PSTOP pointers

determine the size of the buffer ring. The CURR pointer determines the location of the next packet to be

received and the BNRY pointer determines the location of the next packet to be removed. When packets

are received, the CURR pointer moves to the next location (in the direction of rotation) and the BNRY

follows the CURR pointer.

However, the PSTART and PSTOP remains the same throughout the

procedure.

To receive packets, buffers are linked as necessary to accomodate the incoming packets. Up to 256 buffers

can be linked together in a single ring. Each buffer is 256 bytes. That effectively yields a maximum of 64K

bytes for the entire ring. Therefore, the theoretical maximum space between PSTART and PSTOP is 64K

and all the pointers refer to 256 byte boundaries (see figure 7).

Buffer # 1

Buffer # 2

Buffer # 3

Buffer # n

Buffer Ram (up to 64 KB)

Page Start Address

Page Stop

Receive Buffer Ring

n

3

2

1

4

256 Bytes

Direction

of Rotation

Address

Direction

of Rotation

Figure 7. Receive Buffer Ring