UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

5



Address

CE1

CE2

WE

Dout

Din

Data Valid

High-Z

(4)

(4)

WRITE CYCLE 2 (

1

Data Valid

Address

CE1

CE2

WE

Dout

Din

High-Z

Notes :

1.

WE or

1

CE must be HIGH or CE2 must be LOW during all address transitions.

2. A write occurs during the overlap of a low

1

CE , a high CE2 and a low

WE .

3. During a

and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the

1

CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state.