CS5394

DS258PP4

15

Analog Inputs

AINR-, AINR+ - Differential Right Channel Analog Inputs, Pins 26 and 27.

Analog input connections for the right channel differential inputs. Nominally 4.0 Vpp

differential for full-scale digital output.

AINL-, AINL+ - Differential Left Channel Analog Inputs, Pins 4 and 5.

Analog input connections for the left channel differential inputs. Nominally 4.0 Vpp differential

for full-scale digital output.

Analog Outputs

VCOM - Common Mode Voltage Output, Pin 2.

Nominally +2.5 volts. Requires a 10

µF electrolytic capacitor in parallel with 0.1 µF ceramic

capacitor for decoupling to AGND. Caution is required if this output be used to bias the analog

input buffer circuits. Refer to the CDB5394 as an example.

VREF - Voltage Reference Output, Pin 1.

Nominally +4 volts. Requires a 100

µF electrolytic capacitor in parallel with 0.1 µF ceramic

capacitor for decoupling to AGND.

Digital Inputs

ADCTL - Analog Control Input, Pin 6.

Must be connected to DACTL. This signal enables communication between the analog and

digital circuits.

DFS - Digital Format Select, Pin 18.

The relationship between LRCK, SCLK and SDATA is controlled by the DFS pin. When high,

the serial output data format is I

CAL - Calibration, Pin 10.

Activates the calibration of the tri-level delta-sigma modulator on the rising edge of the CAL

input.

MCLKA - Analog Section Input Clock, Pin 7.

This clock is internally divided and controls the delta-sigma modulators. An MCLKA

frequency of 12.288 MHz sets a modulator sampling rate of 3.072 MHz and a output sample

rate of 48 kHz. MCLKA must be connected to MCLKD.