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CS5394KS Datasheet(PDF) 12 Page - Cirrus Logic

Part # CS5394KS
Description  117 DB 48KHZ AUDIO A/D CONVERTER
PDF  22 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5394KS Datasheet(HTML) 12 Page - Cirrus Logic

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CS5394
12
DS258PP4
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care
must be taken to achieve simultaneous sampling. It
is recommended that the rising edge of the CAL
signal be timed with a falling edge of MCLK to en-
sure that all devices will initiate a calibration and
synchronization sequence on the same rising edge
of MCLK. The absence of re-timing of the CAL
signal can result in a sampling difference of one
MCLK period.
Grounding and Power Supply Decoupling
As with any high resolution converter, the ADC re-
quires careful attention to power supply and
grounding arrangements if its potential perfor-
mance is to be realized. Figure 1 shows the recom-
mended power arrangements, with VA and VL
connected to a clean +5 V supply. VD, which pow-
ers the digital filter, may be run from the system
+5 V logic supply. Alternatively, VD may be pow-
ered from the analog supply via a ferrite bead. In
this case, no additional devices should be powered
from VD. Decoupling capacitors should be as near
to the ADC as possible, with the low value ceramic
capacitor being the nearest.
The printed circuit board layout should have sepa-
rate analog and digital regions and ground planes,
with the ADC straddling the boundary. All signals,
especially clocks, should be kept away from the
VREF pin in order to avoid unwanted coupling into
the modulators. The VREF decoupling capacitors,
particularly the 0.1 µF, must be positioned to mini-
mize the electrical path from VREF and pin 3,
AGND. The CDB5394 evaluation board demon-
strates the optimum layout and power supply ar-
rangements, as well as allowing fast evaluation of
the ADC.
To minimize digital noise, connect the ADC digital
outputs only to CMOS inputs.
PERFORMANCE
Digital Filter
Figures 5-8 show the performance of the digital fil-
ter included in the ADC. All plots are normalized
to Fs. Assuming a sample rate of 48 kHz, the 0.5
frequency point on the plot refers to 24 kHz. The
filter frequency response scales precisely with Fs.



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