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DS14285 Datasheet(PDF) 21 Page - Dallas Semiconductor |
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DS14285 Datasheet(HTML) 21 Page - Dallas Semiconductor |
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21 / 25 page  DS14285/DS14287 21 of 25 POWER-DOWN/POWER-UP TIMING POWER-DOWN/POWER-UP TIMING PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CS at VIH before Power-Down tPD 0 µs VCC slew from 4.5V to 0V ( CS at VIH) tF 300 µs VCC slew from 0V to 4.5V ( CS at VIH) tR 100 µs CS at VIH after Power-Up tREC 20 200 ms Chip Enable Propagation Delay to External SRAM tCED 10 ns (tA = 25 °C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention for DS14287 tDR 10 years 10 NOTE: The real-time clock will keep time to an accuracy of+1 minute per month during data retention time for the period of tDR. WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. |
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