8

LT1910

sn1910 1910fs

supply at the same point as the positive end of the sense

resistor.

The drain sense threshold voltage has a positive tempera-

ture coefficient, allowing PTC sense resistors to be used

should be based on the minimum threshold voltage:

Thus the 0.02

Ω drain sense resistor in Figure 3 will yield

a minimum trip current of 2.5A. This simple configuration

is appropriate for resistive or inductive loads that do not

generate large current transients at turn-on.

Automatic Restart Period

length of time the power MOSFET is held off following a

current limit trip. Curves are given in the Typical Perfor-

mance Characteristics to show the restart period for

50ms restart period.

Defeating Automatic Restart

Some applications are required to remain off after a fault

occurs. When the LT1910 is being driven from CMOS

logic, this can be easily implemented by connecting resis-

tor R2 between the IN and TIMER pins as shown in

Figure 4. R2 supplies the sustaining current for an internal

SCR which latches the TIMER pin LOW under a fault

condition. The FAULT pin is set active LOW when the

TIMER pin falls below 3.3V. This keeps the MOSFET gate

from turning ON and the FAULT pin from resetting HIGH

FAULT pin from glitching whenever the IN pin recycles to

turn on the MOSFET unsuccessfully under an existing fault

condition.

Inductive vs Capacitive Loads

Turning on an inductive load produces a relatively benign

ramp in MOSFET current. However, when an inductive

load is turned off, the current stored in the inductor needs

somewhere to decay. A clamp diode connected directly

across each inductive load normally serves this purpose.

If a diode is not employed, the LT1910 clamps the MOSFET

gate 0.7V below ground. This causes the MOSFET to

Capacitive loads exhibit the opposite behavior. Any load

that includes a decoupling capacitor will generate a cur-

With large electrolytic capacitors, the resulting current

spike can play havoc with the power supply and false trip

the current sense comparator.

Turn-on

∂V/∂t is controlled by the addition of the simple

network shown in Figure 5. This network takes advantage

of the fact that the MOSFET acts as a source follower

during turn-on. Thus the

∂V/∂t on the source can be

controlled by controlling the

∂V/∂t on the gate.

APPLICATIO S I FOR ATIO

IN

TIMER

FAULT

5V

FAULT OUTPUT

R1

5.1k

ON = 5V

OFF = 0V

LT1910

GND

1

1910 F04

4

R2

2k

CT

1

µF

2

3

5V

CMOS

LOGIC

Figure 4. Latch-Off Configuration (Autorestart Defeated)

SENSE

8

6

LT1910

1

GND

Q1

IRFZ34

15V

1N4744

C2

50

µF

50V

1910 F05

0.01

Ω

+

+

1N4148

24V

CURRENT LIMIT

DELAY NETWORK

C1

1N4148

R1

100k

R2

100k

∂V/∂t CONTROL NETWORK

GATE

5

Figure 5. Control and Current Limit Delay