ST72561 datasheet(168/262 Pages) STMICROELECTRONICS

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ST72561

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LIN

SCI

 SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)

CONTROL REGISTER 3 (SCICR3)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7= Reserved, must be ket cleared.

Bit 6 = LINE LIN Mode Enable.

This bit is set and cleared by software.

0: LIN Mode disabled

1: LIN Master mode enabled

The LIN Master mode enables the capability to

send LIN Synch Breaks (13 low bits) using the

SBK bit in the SCICR2 register

.In transmission, the LIN Synch Break low phase

duration is shown as below:

Bits 5:4 = Reserved, forced by hardware to 0.

These bits are not used.

Bit 3= CLKEN Clock Enable.

This bit allows the user to enable the SCLK pin.

0: SLK pin disabled

1: SLK pin enabled

Bit 2= CPOL Clock Polarity.

This bit allows the user to select the polarity of the

clock output on the SCLK pin. It works in conjonc-

tion with the CPHA bit to produce the desired

clock/data relationship (see Figure 92 & Figure 93)

0: Steady low value on SCLK pin outside transmis-

sion window.

1: Steady high value on SCLK pin outside trans-

mission window.

Bit 1= CPHA Clock Phase.

This bit allows the user to select the phase of the

clock output on the SCLK pin. It works in conjonc-

tion with the CPOL bit to produce the desired

clock/data relationship (see Figure 92 & Figure 93)

0: SCLK clock line activated in middle of data bit.

1: SCLK clock line activated at beginning of data

bit.

Bit 0= LBCL Last bit clock pulse.

This bit allows the user to select whether the clock

pulse associated with the last data bit transmitted

(MSB) has to be output on the SCLK pin.

0: The clock pulse of the last data bit is not output

to the SCLK pin.

1: The clock pulse of the last data bit is output to

the SCLK pin.

Note: The last bit is the 8th or 9th data bit transmit-

ted depending on the 8 or 9 bit format selected by

the M bit in the SCICR1 register.

Table 25. SCI clock on SCLK pin

Note: These 3 bits (CPOL, CPHA, LBCL) should

not be written while the transmitter is enabled.

LINE

CLKEN

CPOL

CPHA

LBCL

LINE

Number of low bits sent

during a LIN Synch Break

Data

format

M bit

LBCL bit

Number of clock

pulses on SCLK

8 bit

9 bit

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